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參數(shù)資料
| 型號： | STV7612 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PLASMA DISPLAY PANEL DATA DRIVER |
| 中文描述： | 等離子顯示器數(shù)據(jù)驅(qū)動 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 465K |
| 代理商： | STV7612 |
STV7612
ADCS 7399251
13/18
AC TIMINGS REQUIREMENTS
(V
CC
= 4.5 V to 5.5 V, T
amb
= -20 to +85°C, input signals max leading edge & trailing edge (t
R
, t
F
) = 10 ns)
Symbol
Parameter
AC TIMINGS CHARACTERISTICS
(V
CC
= 5 V, V
PP
= 90 V
,
V
SPP
= 0 V, V
SSLOG
= 0 V, V
SSSUB
= 0 V, T
amb
= 25°C)
(V
IL(Max.)
= 0.2 Vcc, V
IH(Min.)
= 0.8 V
CC
, V
OH
= 4.0V, V
OL
= 0.4 V, unless otherwise specified)
Symbol
Parameter
Note 7
For IC in cascading configuration and in case a time delay is inserted on the clock signal of the cascaded IC, the
maximum value of this time delay must be set at the minimum value of t
PHL1,
t
PLH1
(
Figure 7
).
Note 8
One output among 96, loading capacitor C
L
= 50pF, other outputs at low level.
Min.
Typ.
Max.
Unit
t
WHCLK
Duration of clock (CLK) pulse at high level
15
-
-
ns
t
WLCLK
Duration of clock (CLK) pulse at low level
15
-
-
ns
t
SDAT
Set-up Time of data input before clock (low to high) transition
10
-
-
ns
t
HDAT
Hold Time of data input after clock (low to high) transition
10
-
-
ns
t
SFR
F/R (FOR/REV) Set-up Time before clock (low to high) transition
100
ns
t
DSTB
Minimum Delay to latch STB after clock (low to high) transition
10
-
-
ns
t
SSTB
Minimum Delay to latch STB before clock (low to high) transition
10
-
-
ns
t
STB
Latch STB Low Level Pulse Duration
20
-
-
ns
t
BLK
Blanking BLK Pulse Duration
500
-
-
ns
t
POL
Polarity POL Pulse Duration
500
-
-
ns
Min.
Typ. Max. Unit
t
CLK
Data clock Period
50
-
-
ns
t
RDAT
t
FDAT
t
PHL1
t
PLH1
Logical Data Output Rise Time (CL=10pF)
-
12
20
ns
Logical Data Output Fall Time (CL=10pF)
-
11
20
ns
Delay of logic data output (high to low transition) after clock (CLK) transition
Note 7
Delay of logic data output (low to high transition) after clock (CLK) transition
Note 7
15
15
35
35
50
50
ns
ns
t
PHL2
t
PLH2
t
PHL3
t
PLH3
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
-
-
135
80
180
180
ns
ns
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
-
-
115
70
165
165
ns
ns
t
PHL4
t
PLH4
Delay of power output change (high to low transition) to Blank or Polarity (BLK, POL)
transition
Delay of power output change (low to high transition) to Blank or Polarity (BLK, POL)
transition
-
-
100
55
160
160
ns
ns
t
ROUT
Power Output Rise Time (
Note 8
)
-
50
150
ns
t
FOUT
Power Output Fall Time (
Note 8
)
-
80
200
ns
3
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|---|---|
| STV7620WAF | PLASMA DISPLAY PANEL DATA DRIVER |
| STV7620 | PLASMA DISPLAY PANEL DATA DRIVER |
| STV7620F | PLASMA DISPLAY PANEL DATA DRIVER |
| STV7620M | PLASMA DISPLAY PANEL DATA DRIVER |
| STV7620S | PLASMA DISPLAY PANEL DATA DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STV7612/WAF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PLASMA DISPLAY PANEL DATA DRIVER |
| STV7617 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PLASMA DISPLAY PANEL SCAN DRIVER |
| STV7617D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PLASMA DISPLAY PANEL SCAN DRIVER |
| STV7617U | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PLASMA DISPLAY PANEL SCAN DRIVER |
| STV7618 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PLASMA DISPLAY PANEL DATA DRIVER |
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