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參數(shù)資料
| 型號(hào)： | STV5348DH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MONOCHIP TELETEXT AND VPS DECODER WITH 8 INTEGRATED PAGES |
| 中文描述： | MONOCHIP圖文電視解碼器及車輛定位系統(tǒng)集成8頁 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 684K |
| 代理商： | STV5348DH |
FUNCTIONAL DESCRIPTION
(continued)
III - VPS DATA
(see Table 2)
VPS data are stored in row 25 chapter 5 as shown
in Table 2 when VPS enable bit (D4 of R8 register)
is set. VPS data bits are decoded and stored in a
received area with biphase error bit.
8/30/2 data are stored as received (without ham-
ming decoding) in Row 23 chapter 5 according to
Table 2. .
8/30 packet and VPS data decoding is the respon-
sibility of the control software. The decoder simply
stores transmitted data.
IV - I
2
C Bus Register Map
(see Table 3)
Registers R0 to R10 are write only whilst R11A is
Table 2 :
PDC Data Storage in Chapter 5
a read/write and R11B is read only.
The automatic succession on a byte by byte basis
is indicated by the arrows in Table 3.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows : all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to "alpha white" hexadecimal value 07H.
Column
8/30/2 (Row 23)
VPS (Row 25)
0
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Initial Page
Received Page Information
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
B11
B12
B13
B14
B15
Column
8/30/2 (Row 23)
VPS (Row 25)
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Status Display
B4
B5
5
D7
D6
D5
D4
D3
D2
D1
D0
X24
POSITION
FREE
RUNNING
PLL
0
DISABLE
ROLLING
HEADER
(1)
EVEN
OFF
(1)
SEL 11B
R0
Mode 0
(1)
7 + P/
8 BIT
ACQ.
ON/OFF
GHOST
ROW
ENABLE
DEW/
FULL
FIELD
TCS
ON
T1
T0
R1
Mode 1
(1)
BANK
SELECT
A2
ACQ.
CCT
A1
ACQ.
CCT
A0
TB
START
COLUMN
SC2
START
COLUMN
SC1
START
COLUMN
SC0
R2
Page request address
(1)
(1)
(1)
PRD4
PRD3
PRD2
PRD1
PRD0
R3
Page request data
(1)
(1)
(1)
(1)
(1)
A2
A1
A0
R4
Display chapter
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R5
Display control (normal)
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R6
Display control
(newsflash / subtitle)
STATUS
ROW
BTM/TOP
CURSOR
ON/OFF
CONCEAL/
REVEAL
TOP/
BOTTOM
SINGLE/
DOUBLE
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
R7
Display mode
(1)
(1)
(1)
VPS
ENABLE
CLEAR
MEM.
A2
A1
A0
R8
Active chapter
(1)
(1)
(1)
R4
R3
R2
R1
R0
R9
Active row
(1)
(1)
C5
C4
C3
C2
C1
C0
R10
Active column
D7
(R/W)
D6
(R/W)
D5
(R/W)
D4
(R/W)
D3
(R/W)
D2
(R/W)
D1
(R/W)
D0
(R/W)
R11A
Active data
60Hz
0
0
0
0
0
DATA
QUAL
V
CS
QUAL
R11B
Status
5
(1) Reserved register bits : must be set to 0
Table 3 :
Register Specification
STV5348 - STV5348/H - STV5348/T
9/22
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