
D0
D1
D2
D3
D4
D5
D6
D7
PU0
PU1
PU2
PU3
HAM
0
0
0
0
PT0
PT1
PT2
PT3
HAM
0
0
0
1
MU0
MU1
MU2
MU3
HAM
0
0
0
2
MT0
MT1
MT2
C4
HAM
0
0
0
3
HU0
HU1
HU2
HU3
HAM
0
0
0
4
HT0
HT1
C5
C6
HAM
0
0
0
5
C7
C8
C9
C10
HAM
0
0
0
6
C11
C12
C13
C14
HAM
0
0
0
7
MAG0
MAG1
MAG2
0
FOUND
0
0
0
8
0
0
0
0
0
PBLF
0
0
9
COLUMN
Page number : - MAG = magazine,PU = page units, PT= page tens.
Page sub-code : - MU = minutes units, MT= minutes tens, HU = hours units, HT = hourstens.
PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
5
Table 1 :
Row25 receivedpage controldata format
8/30 READING
8/30 packetis read at row 23 equivalent address.
R8 register must be programmed with D3, D2,
D0 = 0 and D2 = 1 (8/30selection).
R9 register mustbe programmedwith 23 (17h).
R10 register value corresponds to the position of
the byte to be read (from 0 to 39).
R11Acontents the value of the needed byte.
D7
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
EVEN
OFF
TC
SEL11B
R0
Mode 0
TA
7 + P/
8 BIT
ACQ.
ON/OFF
8/30
ENABLE
DEW/
FULL
FIELD
TCS
ON
T1
T0
R1
Mode 1
*
*
ACQ
CCT
A1
ACQ.
CCT
A0
TB
START
COLUMN
SC2
START
COLUMN
SC1
START
COLUMN
SC0
R2
Page request adress
*
*
*
PRD4
PRD3
PRD2
PRD1
PRD0
R3
Page request data
*
*
*
*
*
*
A1
A0
R4
Display chapter
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R5
Display control(normal)
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
R6
Display control
(newsflash / subtitle)
STATUS
ROW
BTM/TOP
CURSOR
ON
CONCEAL/
REVEAL
TOP/
BOTTOM
SINGLE/
DOUBLE
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
R7
Display mode
*
*
*
*
CLEAR
MEM.
8/30
SELECT
A1
A0
R8
Active chapter
*
*
*
R4
R3
R2
R1
R0
R9
R10
Active row
Active column
*
*
C5
C4
C3
C2
C1
C0
D7
(R/W)
D6
(R/W)
D5
(R/W)
D4
(R/W)
D3
(R/W)
D2
(R/W)
D1
(R/W)
D0
(R/W)
R11A
Active data
60Hz
0
0
0
0
0
0
VCS
signal
quality
R11B
Status
* Reserved register bits : must beset to 0
5
Table 2 :
Registerspecification
REGISTERMAP (see Table 2)
RegistersR0 to R10 are write onlywhilst R11Aisa
read/writeand R11Bis aread onlyregister respect
to the microprocessor.
The automatic succession on a byte basis is indi-
cated by the arrows in Table 2.
In the normal operating mode TA, TB and TC
should be set to logic level 0.
After power-up thecontents of the registers areas
follows: all bits in registers R0 to R11Aarecleared
to zero with the exception of bits D0 and D1 in
registersR5 and R6 whichare set to logical one.
After power-up all the memory bytes are preset to
hexadecimalvalue20H(space)withthe exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alphawhite” hexadecimalvalue 07 H.
STV5342
13/20