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參數(shù)資料
| 型號： | STV1601A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SERIAL INTERFACE TRANSMISSION ENCODER |
| 中文描述： | 串行接口傳輸編碼器 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 244K |
| 代理商： | STV1601A |
80%
20%
t
t
r
f
1
Figure9 :
t
r
, t
f
Definition
50%
t
c
t
d
t
w
c
t /2
c
t /2
1
Figure10 :
t
d
, t
W
Definition
DESCRIPTION
STV1601A internally generates a 10 times clock
frequencylocked to the parallel input clock thanks
to abuilt-in PLLand convertsinputparalleldatainto
Figure11 :
PhaseRelation between Clock andData
serial data.
Toeaseclockextractionat thereceiving end,serial
dataisscrambled.Tominimize polarityeffect,serial
datais thenconvertedto NRZI andoutput in differ-
ential mode.
APLLlock detectioncircuit onlyenables the serial
output when locked.
1. Phase relationbetween input parallelclock
and data
The phase relationbetween the parallel clock and
the data is shown in Figure11. Both clockand data
are differentialinputs
Parallelclockanddataaresuchthattherisingedge
of PCX should be atthe middleof the data. Aclock
havingthesamephase asPCX is internallygener-
atedin orderto latch the data.
2. TTL input operation
Parallel clock and data can be either TTL or ECL
inputs. Touse asTTL inputs VCC(Pin 29) shallbe
connected to +5V. A fixed bias of +1.4V shall be
applied to PCY and DnY (n = 0 to 9). TTL signals
and their parallel clock will be provided through
1kW resistors to each ”X”input. These1kW resis-
tors are effective to minimize the influence of the
TTLinput signals to the jitter characteristics of the
serial outputsignal. For 8-bit data, unused LSB(s)
must be fixed Low. Fixed bias value can be higher,
for example,2.5V in caseof CMOS inputs.
PCX (Input)
DATA (Input)
PCX (Output)
1
29
30
31
5
7
26
25
Parallel
Clock
Parallel
Data
+ 5V
+ 1.4V for TTL
+ 2.5V forCMOS
D0Y
D0X
D9Y
D9X
PCY
PCX
V
CC
TTL ParallelSignal
STV1601A
1k
1k
1k
1
Figure12 :
TTLInput Operation
STV1601A
11/17
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