參數(shù)資料
型號(hào): STR911FM44X6T
廠商: 意法半導(dǎo)體
英文描述: ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
中文描述: ARM966E - ?商標(biāo)16/32位閃存微控制器與以太網(wǎng),USB,加拿大,交流電機(jī)控制,4個(gè)定時(shí)器,模數(shù)轉(zhuǎn)換器,RTC和DMA的
文件頁(yè)數(shù): 22/73頁(yè)
文件大小: 595K
代理商: STR911FM44X6T
Functional overview
STR91xF
22/73
Figure 3.
JTAG chaining inside the STR91xF
2.15.1 In-system-programming
The JTAG interface is used to program or erase all memory areas of the STR91xF device. The
pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid
instructions while the Flash memories are being programmed.
Note that the 32 bytes of OTP memory locations cannot be erased by any means once
programmed by JTAG ISP or the CPU.
2.15.2 Boundary scan
Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority
of pins of the STR91xF for circuit board test during manufacture of the end product. STR91xF
pins that are not serviced by boundary scan are the following:
JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK
Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC
Tamper detect input pin TAMPER_IN (128-pin packages only)
2.15.3 CPU debug
The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the STR91xF
to be debugged through the JTAG interface. This provides advanced debugging features
making it easier to develop application firmware, operating systems, and the hardware itself.
JTDI
JTMS
JTCK
JTDO
TDI
TMS
TCK
TDO
TDO
TMS
TCK
TDI
JTAG TAP CONTROLLER #1
JTAG TAP CONTROLLER #3
BURST FLASH
MEMORY DIE
ARM966ES DIE
BOUNDARY SCAN
STR91xx
JTRSTn
TRST
TDI
TMS
TCK
TDO
JTAG TAP CONTROLLER #2
CPU DEBUG
TRST
JRTCK
TRST
MAIN FLASH
SECONDARY FLASH
JTAG
Instruction
register length:
5 bits for TAP #1
4 bits for TAP #2
JTAG
Instruction
register length
is 8 bits
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