參數(shù)資料
型號: STPD0166BTA3
廠商: 意法半導(dǎo)體
元件分類: DC/DC變換器
英文描述: RP15 (F) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 3.3V; 2:1 Wide Input Voltage Range; 15 Watts Output Power; 1.6kVDC Isolation; UL Certified; Fixed Operating Frequency; Six-Sided Continuous Shield; Standard 50.8 x25.4x10.2mm Package; Efficiency to 88%
中文描述: PC兼容嵌入式微處理器
文件頁數(shù): 1/48頁
文件大?。?/td> 762K
代理商: STPD0166BTA3
Issue 1.7
1/48
STPC CLIENT
PC Compatible Embedded Microprocessor
February 8, 2000
Figure 1. Logic Diagram
POWERFUL X86 PROCESSOR
64-BIT 66MHz BUS INTERFACE
64-BIT DRAM CONTROLLER
SVGA GRAPHICS CONTROLLER
UMA ARCHITECTURE
VIDEO SCALER
VIDEO OUTPUT PORT
VIDEO INPUT PORT
CRT CONTROLLER
135MHz RAMDAC
2 OR 3 LINE FLICKER FILTER
SCAN CONVERTER
PCI MASTER / SLAVE / ARBITER
ISA MASTER/SLAVE
IDE CONTROLLER
DMA CONTROLLER
INTERRUPT CONTROLLER
TIMER / COUNTERS
POWER MANAGEMENT
STPC CLIENT OVERVIEW
The STPC Client integrates a standard 5th
generation x86 core, a DRAM controller,
graphics
subsystem,
a
support
logic including
controllers
to
provide
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
colour space conversion of the video input stream
and mixing of the video stream with non-video
data from the frame buffer. The chip also includes
anti-flicker filters to provide a stable, high-quality
Digital TV output.
The STPC Client is packaged in a 388 Plastic Ball
Grid Array (PBGA).
a
video
PCI, ISA, and
a
single
pipeline,
and
IDE
Consumer
PBGA388
x86
Core
Host I/F
DRAM
VIP
PCI
PCIBUS
ISA
EID
PCI
ISABUS
CRT
HW
Monitor
TVOutput
SYNCOutput
Col-
Col-
our
Vid-
2D
CCIRInput
EIDE
Anti-
IPC
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