參數(shù)資料
型號(hào): STPCINDUSTRIAL
廠商: 意法半導(dǎo)體
英文描述: PC Compatible Embedded Microprocessor
中文描述: PC兼容嵌入式微處理器
文件頁數(shù): 18/55頁
文件大小: 787K
代理商: STPCINDUSTRIAL
PIN DESCRIPTION
18/55
Issue 1.1
Table 3-2. Definition of Signal Pins
Signal Name
BASIC CLOCKS AND RESETS
SYSRSTI#*
SYSRSTO#*
XTALI
XTALO
PCI_CLKI*
PCI_CLKO
ISA_CLK, ISA_CLK2X
CLK14M
HCLK*
DEV_CLK*
GCLK2X
DCLK
V
DD
_xxx_PLL
Dir
Description
Qty
I
System Reset / Power good
Reset Output to System
14.3MHz Crystal Input
14.3MHz Crystal Output
33MHz PCI/CardBus Input Clock
33MHz PCI/CardBus Output Clock
ISA Clock x1 and x2 (also Multiplexer Select Line ForIPC)
ISA bus synchronisation clock
33 / 66MHz Host Clock (Test)
24MHz Peripheral Clock
80MHz Graphics Clock
135MHz Dot Clock
Power Supply for PLL Clocks
1
1
1
1
1
1
2
1
1
1
1
1
O
I
O
I
O
O
O
I/O
O
I/O
I/O
MEMORY INTERFACE
MA[11:0]
RAS#[3:0]
CAS#[7:0]
MWE#
MD[63:0]
I/O
O
O
O
I/O
Memory Address
Row Address Strobe
Column Address Strobe
Write Enable
Memory Data
12
4
8
1
64
LOCAL BUS INTERFACE (COMBINED WITH ISA BUS )
PA[21:0]*
PD[15:0]*
PRDY#*
PWR#[1:0]*
PRD#[1:0]*
FCS#[1:0]*, IOCS#[3:0]*
O
I/O
I
O
O
O
Address Bus [21:0]
Data Bus [15:0]
Ready
Memory and I/O Write signals
Memory and I/O Read signals
Flash Memory and I/O Chip Select
22
16
1
2
2
6
ISA BUS INTERFACE (COMBINED WITH LOCAL BUS, PARALLEL PORT, SERIAL INTERFACE)
LA[23:17]*
O
Unlatched Address
SA[19:0]*
O
Latched Address
SD[15:0]*
I/O
Data Bus
IOCHRDY*
I
I/O Channel Ready
ALE*
O
Address Latch Enable
BHE#*
O
System Bus High Enable
MEMR#*, MEMW#*
I/O
Memory Read & Write
SMEMR#*, SMEMW#*
O
System Memory Read and Write
IOR#*, IOW#*
I/O
I/O Read and Write
MASTER#*
I
Add On Card Owns Bus
MCS16#*, IOCS16#*
I
Memory Chip Select 16, I/O Chip Select 16
REF#*
I
Refresh Cycle
AEN*
O
Address Enable
IOCHCK#*
I
I/O Channel Check (ISA)
RTCRW#*
O
RTC Read / Write#
RTCDS#*
O
RTC Data Strobe
RTCAS#*
O
RTC Address Strobe
7
20
16
1
1
1
2
2
2
1
2
1
1
1
1
1
1
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