參數(shù)資料
型號: STPCI2HEYI
英文描述: PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述: 周邊(多功能)控制器
文件頁數(shù): 45/71頁
文件大小: 1071K
代理商: STPCI2HEYI
ELECTRICAL SPECIFICATIONS
Issue 2.4 - February 11, 2002
45/69
tRCH
tRCS
tRP
tWCH
tWCS
tWRH
tWRP
tAR
tRAD
tRAL
tWCR
tRWL
tCWL
tDHR
tRPC
tCRS
tCHR
tCSH
Read Command Hold Time
Read Command Setup Time
RAS Precharge Time
Write Command Hold Time
WE Command Setup Time
WE Hold Time
WE Setup Time
Column Address Hold Time from RAS
RAS to valid Column Address Delay
Column Address to RAS Setup Time
Write Command Hold Reference to RAS
Write Command to RAS Setup Time (Note 2)
Write Command to CAS Setup Time (Note 2)
Data Hold Reference to RAS
RAS High to CAS Low Precharge
CAS Before RAS Setup Time
CAS Before RAS Hold Time
CAS Hold Time after RAS
Note 1; T
Cycle
x n
CAS
+ (t
Data off
- t
CAS out
)
Where T
Cycle
is the number of clock cycles.
n
CAS
is the number of CAS Cycles (see
Section 6.7.
)
T
Dataoff
is the Generic Datahold
t
CAS Out
the CLK (either HCLK or GCLK2X) to CAS Low.
T
Dataoff
and t
CAS Out
are used to refine the timing programming.
1T
Cycles
1T
Cycles
2T
Cycles
1T
Cycles
1T
Cycles
Note 2
1T
Cycles
1T
Cycles
1T
Cycles
2T
Cycles
1T
Cycles
1T
Cycles
1T
Cycles
3T
Cycles
1T
Cycles
1T
Cycles
1T
Cycles
1T
Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4-6. AC Memory Timing Characteristics
Parameter
Min
Max
Units
Note 2; Value to be derived from CAS pulse width which is programmable (see
Section 6.7.
).
Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X
Table 4-7. Graphics Adapter (VGA) AC Timing
Name
t18
t19
Parameter
DCLK to VSYNC valid
DCLK to HSYNC valid
Min
Max
27
27
Unit
ns
ns
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