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參數(shù)資料
| 型號： | STPCI0180BTC3 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 微處理器 |
| 英文描述： | PC Compatible Embedded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁數(shù)： | 12/55頁 |
| 文件大?。?/td> | 787K |
| 代理商： | STPCI0180BTC3 |
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STRAP OPTION
12/55
Issue 1.1
2.1 STRAP OPTION REGISTER DESCRIPTION
2.1.1 STRAP REGISTER 0 INDEX 4AH (STRAP0)
Bits 7-0, This register reflect the status of pins MD[7:0] respectively. They are expected to be connected
on the system board to the SIMM configuration pins as follows:
Note that the SIMM speed and type information read here is meant only for the software and is not used
by thehardware. The software must program the Host and graphics DRAM controller configuration regis-
ters appropriately based on these bits.
This register defaults to the values sampled on MD[7:0] pins after reset.
MD 39
MD 40
MD 41
MD 42
MD 43
MD 44
MD 45
MD 46
MD 47
MD 48
Reserved
PCMCIA or PCI i/f
Local Bus or ISA i/f
Key Board & Mouse
Parallel Port
UART1
UART2
Reserved
Reserved
Outputs on RFU pads
Pull up
User defined
User defined
User defined
User defined
User defined
User defined
Pull down
Pull down
User defined
3C,bit 0
3C,bit 1
3C,bit 2
3C,bit 3
3C,bit 4
3C,bit 5
3C,bit 6
3C,bit 7
3D,bit 0
PCI
ISA
PCMCIA
Local Bus
Internal
Internal
Internal
Internal
External
External
External
External
Serial Port
TFT
Disable
Not Availa-
ble
Not Availa-
ble
Not Availa-
ble
Not Availa-
ble
Enable
MD 49
Cardbus Socket
5V Availability
3D,bit 1
User defined
Available
MD 50
3.3V Availability
3D,bit 2
User defined
Available
MD 51
x.xV Available
3D,bit 3
User defined
Available
MD 52
y.yV Available
3D,bit 4
User defined
Available
MD 53
MD 56
MD 57
MD 58
MD 59
Reserved
Reserved
Reserved
Reserved
Reserved
Pull uo
Pull up
Pull down
Pull up
Pull down
Bit Sampled
Bit 7
Bits 6-5
Bit 4
Bits 3-2
Bits 1-0
Description
SIMM 0 DRAM type
SIMM 0 speed
SIMM 1 DRAM type
SIMM 1 speed
Reserved
Memory
Data
Lines
Refer to
Designation
Location
Actual
Settings
Set to ’0’
Set to ’1’
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| STPCI2GDYIE | 制造商:STMicroelectronics 功能描述: |
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