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參數(shù)資料
| 型號(hào)： | STPC4HEBC |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | X86 Core PC Compatible Information Appliance System-on-Chip |
| 中文描述： | x86內(nèi)核的PC兼容的信息家電系統(tǒng)級(jí)芯片 |
| 文件頁(yè)數(shù)： | 1/93頁(yè) |
| 文件大小： | 1406K |
| 代理商： | STPC4HEBC |
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STPC
CONSUMER-II
X86 Core PC Compatible Information Appliance System-on-Chip
Release 1.5 - January 29, 2002
1/93
Figure 0-1. Logic Diagram
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POWERFUL x86 PROCESSOR
64-BIT SDRAM UMA CONTROLLER
VGA & SVGA CRT CONTROLLER
135 MHz RAMDAC
2D GRAPHICS ENGINE
VIDEO INPUT PORT
VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
TV OUTPUT
- THREE-LINE FLICKER FILTER
- ITU-R 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
PCI MASTER / SLAVE / ARBITER
ISA MASTER / SLAVE
OPTIONAL 16-BIT LOCAL BUS INTERFACE
EIDE CONTROLLER
I2C INTERFACE
IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
POWER MANAGEMENT UNIT
JTAG IEEE1149.1
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DESCRIPTION
The STPC Consumer-II integrates a standard 5th
generation x86 core, a Synchronous DRAM
controller, a graphics subsystem, a video pipeline,
and support logic including PCI, ISA, and IDE
controllers to provide a single consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing memory
between the CPU, the graphics and the video.
The STPC Consumer-II is packaged in a 388
Plastic Ball Grid Array (PBGA).
PBGA388
STPC Consumer II
x86
Core
Host
I/F
SDRAM
CTRL
SVGA
CRTC
GE
VIP
PCI
m/s
LB
CTR
PCI Bus
ISA
m/s
IPC
PCI
m/s
ISA Bus
Cursor
Monitor
TV
IDE
I/F
PMU
Video
Pipeline
C Key
K Key
LUT
Local Bus
Encoder
TVO
JTAG
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| STPC4HEBI | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:X86 Core PC Compatible Information Appliance System-on-Chip |
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| STPCATLAS | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:X86 Core PC Compatible System-on-Chip for Terminals |
| STPCC01 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:PC Compatible Embeded Microprocessor |
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