參數(shù)資料
型號: STM6779
廠商: 意法半導體
英文描述: Dual/Triple Ultra-Low Voltage Supervisors with Push-Button Reset (with Delay Option)
中文描述: 雙/三超低電壓的推監(jiān)控,復位按鈕(帶有延遲期權)
文件頁數(shù): 8/25頁
文件大小: 129K
代理商: STM6779
STM6717/6718/6719/6720/6777/6778/6779*/6780*
8/25
OPERATION
Applications Information
1.
Interfacing to Processors with Bi-directional
Reset Pins
Most processors with bi-directional reset pins
can interface directly to the open drain RST
outputs (STM6717/19/77/79). Systems
simultaneously requiring a push-pull RST
output and a bi-directional reset interface can
be in logic contention. To prevent this
contention, connect a 4.7k
resistor between
RST and the processor’s Reset I/O as shown
in
Figure 12.
2.
Ensuring a Valid RST Output Down to
V
CC
= 0V
The STM67xx Supervisors are guaranteed to
be in the correct RST output logic state when
V
CC1
and/or V
CC2
is greater than 0.8V. In
applications which require valid reset levels
down to V
CC
= 0, a pull-down resistor to
active-low outputs (push-pull only, see
Figure
13.
) will ensure that the reset line is valid while
the reset output can no longer sink or source
current. This scheme does NOT work with the
open drain outputs of the STM6717/19/77/79.
The resistor value used is not critical, but it
must be large enough not to load the reset
output when V
CC
is above the reset threshold.
For most applications, 100k
is adequate.
Figure 12. STM67xx Interface to Processor with Bi-directional Reset Pins
Figure 13. Ensuring RST Valid to V
CC
= 0 (Active-Low, Push-Pull Outputs)
AI10425
VCC1
VCC2
VSS
VCC1
STM67xx
RST
To other
system
components
4.7k
VCC2
VSS
Processor
RESET
AI10426
VCC1
VCC1
VSS
STM67xx
RST
R1
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