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參數(shù)資料
| 型號： | STM6315 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | Open Drain Microprocessor Reset(開漏微處理器復(fù)位電路) |
| 中文描述： | 開漏微處理器復(fù)位（開漏微處理器復(fù)位電路） |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 182K |
| 代理商： | STM6315 |
STM6315
Operation
7/21
2
Operation
2.1
Reset output
The STM6315 Microprocessor Reset Circuit has an active-low, open drain reset output. This
output structure will sink current when RST is asserted. Connect a pull-up resistor from RST
to any supply voltage up to 6V (see
Figure 4 on page 6
). Select a resistor value large
enough to register a logic low, and small enough to register a logic high while supplying all
input current and leakage paths connected to the reset output line. A 10k pull-up is sufficient
in most applications.
The STM6315 asserts a reset signal to the MCU whenever V
CC
goes below the reset
threshold (V
RST
), or when the manual reset input (MR) is taken low (see
Figure 5
and
Figure 6 on page 8
). RST is guaranteed valid down to V
CC
= 1.0V.
During power-up, (once V
CC
exceeds the reset threshold) an internal timer keeps RST low
for the reset time-out period, t
rec
. After this interval, RST returns high.
If V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period. Any time V
CC
goes below the reset threshold, the
internal timer clears. The reset timer starts when V
CC
returns above the reset threshold.
2.2
Manual reset input
A logic low on MR asserts RST. RST remains asserted while MR is low, and for t
rec
after it
returns high. The MR input has an internal pull-up resistor 63k
Ω
(typ), allowing it to be left
open if not used.
This input can be driven with TTL/CMOS-logic levels or with open drain/collector outputs.
Connect a standard open push-button switch from MR to V
SS
to create a manual reset
function (see
Figure 4 on page 6
); external debounce circuitry is not required. If the device is
used in a noisy environment, connect a 0.1μF capacitor from MR to V
SS
to provide
additional noise immunity.
2.3
Negative-going V
CC
transients
The STM6315 is relatively immune to negative-going V
CC
transients (glitches).
Figure 12 on
page 11
shows typical transient duration versus reset comparator overdrive (for which the
STM6315 will NOT generate a reset pulse). The graph was generated using a negative
pulse applied to V
CC
, starting at 0.5V above the actual reset threshold and ending below it
by the magnitude indicated (Reset Threshold Overdrive). The graph indicates the maximum
pulse width a negative V
CC
transient can have without causing a reset pulse. As the
magnitude of the transient increases (further below the threshold), the maximum allowable
pulse width decreases. Any combination of duration and overdrive which lies under the
curve will NOT generate a reset signal (see
Figure 12
). A 0.1μF bypass capacitor mounted
as close as possible to the V
CC
pin provides additional transient immunity.
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| STM6322LWY6F | 5-Pin Supervisor with Watchdog Timer and Push-button Reset |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STM6315_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Open drain microprocessor reset |
| STM6315LAW13F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Open drain microprocessor reset |
| STM6315LB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Open drain microprocessor reset |
| STM6315LBW13F | 功能描述:監(jiān)控電路 Open Drain Microprocessor Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| STM6315LDW13F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Open drain microprocessor reset |
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