參數(shù)資料
型號： STM32F103RCH7XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64
封裝： ROHS COMPLIANT, LFBGA-64
文件頁數(shù)： 69/115頁
文件大小： 1225K
代理商： STM32F103RCH7XXX
STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Wakeup time from low-power mode
The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 10.
5.3.8
PLL characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
Table 27.
Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ
Unit
tWUSLEEP
(1)
1.
The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode
Wakeup on HSI RC clock
1.8
s
tWUSTOP
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 s
3.6
s
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 s,
Regulator wakeup from LP mode
time = 5 s
5.4
(1) Wakeup from Standby mode
HSI RC wakeup time = 2 s,
Regulator wakeup from power down
time = 38 s
50
s
Table 28.
PLL characteristics
Symbol
Parameter
Value
Unit
Min
Typ
Max(1)
1.
Based on characterization, not tested in production.
fPLL_IN
PLL input clock(2)
2.
Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
18.0
25
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
72
MHz
tLOCK
PLL lock time
200
s
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相關代理商/技術參數(shù)
參數(shù)描述
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