參數(shù)資料
型號(hào)： STLC7550TQF7
廠商： 意法半導(dǎo)體
英文描述： LOW POWER LOW VOLTAGE ANALOG FRONT END
中文描述： 低電壓低功耗模擬前端
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 174K
代理商： STLC7550TQF7
4 - ANALOG INTERFACE
(9 pins)
4.1 - DAC and ADC Positive Reference
Voltage Output
(V
REFP
)
This pin provides the Positive Reference Voltage
used by the 16-bit converters. The reference volt-
age, V
REF
, is the voltage difference between the
V
REFP
and V
REFN
outputs, and its nominal value is
1.25V. V
REFP
should be externally decoupled with
respect to V
CM
.
4.2 - DAC and ADC Negative Reference
Voltage Output
(V
REFN
)
This pin provides the Negative Reference Voltage
used by the 16-bit converters, and should be exter-
nally decoupled with respect to V
CM
.
4.3 - Common Mode Voltage Output
(V
CM
)
This output pin is the common mode voltage
(AV
DD
- AGND)/2. This output must be decoupled
with respect to GND.
4.4 - Non-inverting Smoothing Filter Output
(OUT+)
This pin is the non-inverting output of the fully
differential analog smoothing filter.
4.5 - Inverting Smoothing Filter Output
(OUT-)
This pin is the inverting output of the fully differential
analog smoothing filter. Outputs OUT+ and OUT-
provide analog signals with maximum peak-to-
peak amplitude 2 x V
REF
, and must be followed by
an external two pole smoothing filter. The external
filter follows the internal single pole switch capaci-
tor filter. The cutoff frequency of the external filter
must be greater than two times the sampling fre-
quency (FS), so that the combined frequency re-
sponse of both the internal and external filters is flat
in the passband . The attenuator of the last output
stage can be programmed to 0dB, 6dB or infinite.
4.6 - Non-inverting Analog Input (IN+)
This pin is the differential non-inverting ADC input.
4.7 - Inverting Analog Input
(IN-)
This pin is the differential inverting ADC input.
These analog inputs (IN+, IN-) are presented to the
Sigma-Delta modulator. The analog input peak-to-
peak differential signal range must be less than
2 x V
REF
, and must be preceded by an external
single pole anti-aliasing filter. The cut-off frequency
of the filter must be lower than one half the over-
sampling frequency. These filters should be set as
close as possible to the IN+ and IN- pins. The gain
of the first stage is programmable (see Table 3).
4.8 - Non-inverting Auxiliary Analog
Input
(AUX IN+)
This pin is the differential non-inverting auxiliary ADC
input. The characteristics are same as the IN+ input.
4.9 - Inverting Auxiliary Analog Input
(AUX IN-)
This pin is the differential inverting auxiliary ADC
input. The characteristics are same as the IN- input.
The input pair (IN+/IN- or AUX IN+/AUX IN-) are
software selectable.
PIN DESCRIPTION
(continued)
ANALOG
MODULATOR
2nd ORDER
MODULATOR
LOW-PASS
(0.425 x sampling
frequency)
HC0
15
OUT+
OUT-
V
CM
V
REFN
V
REFP
IN+
IN-
(0 + 6dB in
diff. input)
DAC 1 BIT
differential
switched
capacitor
filter
LOW-PASS
(0.425 x sampling
frequency)
S
A
ATTEN.
0dB/+6dB/
INFINITE
M/S
FS
SCLK
DOUT
DIN
CLOCK
GENERATOR
XTALIN
XTALOUT
AGND2
AGND1
AV
DD
DV
DD
DGND
STLC7550
RESET
PWRDWN
38
16
6
5
9
8
31
20
29
37
36
30
19
18
28
27
TS
7
MCM
39
HC1
14
17
4
3
42
41
TSTD1
40
AUXIN+
AUXIN-
26
25
MUX
7
BLOCK DIAGRAM
(TQFP44)
STLC7550
5/17
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