參數(shù)資料
型號: STK25CA8-D35
廠商: Electronic Theatre Controls, Inc.
英文描述: 128K x 8 AutoStore nvSRAM CMOS Nonvolatile Static RAM Module
中文描述: 128K的× 8自動(dòng)存儲非易失的CMOS非易失性靜態(tài)隨機(jī)存儲器模塊
文件頁數(shù): 3/8頁
文件大小: 129K
代理商: STK25CA8-D35
STK25CA8
August 1999
6-3
SRAM READ CYCLES #1 & #2
(V
CC
= 5.0V
±
10%)
Note f:
Note g:
Note h:
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
I/O state assumes E, G, < V
and W > V
; device is continuously selected.
Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
SRAM READ CYCLE #2:
E Controlled
f
NO.
SYMBOLS
PARAMETER
STK25CA8-35
STK25CA8-45
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
t
ELQV
t
AVAV
f
t
AVQV
g
t
ACS
Chip Enable Access Time
35
45
ns
2
t
RC
Read Cycle Time
35
45
ns
3
t
AA
Address Access Time
35
45
ns
4
t
GLQV
t
AXQX
g
t
OE
Output Enable to Data Valid
15
20
ns
5
t
OH
Output Hold after Address Change
5
5
ns
6
t
ELQX
t
EHQZ
h
t
LZ
Chip Enable to Output Active
5
5
ns
7
t
HZ
Chip Disable to Output Inactive
13
15
ns
8
t
GLQX
t
GHQZ
h
t
ELICCH
e
t
EHICCL
d, e
t
OLZ
Output Enable to Output Active
0
0
ns
9
t
OHZ
Output Disable to Output Inactive
13
15
ns
10
t
PA
Chip Enable to Power Active
0
0
ns
11
t
PS
Chip Disable to Power Standby
35
45
ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
8
t
GLQX
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
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