參數(shù)資料
型號(hào)： STK22C48W45I
廠商： Electronic Theatre Controls, Inc.
英文描述： 2K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM
中文描述： 2K × 8自動(dòng)存儲(chǔ)非易失QuantumTrap⑩⑩的CMOS非易失性靜態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 7/11頁(yè)
文件大?。?/td> 194K
代理商： STK22C48W45I
STK22C48
December 2002
7
Document Control # ML0004 rev 0.0
The STK22C48 has two separate modes of opera-
tion:
SRAM
mode and nonvolatile mode. In
SRAM
mode, the memory operates as a standard fast
static
RAM
. In nonvolatile mode, data is transferred
from
SRAM
to Nonvolatile Elements (the
STORE
operation) or from Nonvolatile Elements to
SRAM
(the
RECALL
operation). In this mode
SRAM
func-
tions are disabled.
NOISE CONSIDERATIONS
The STK22C48 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1
μ
F connected between V
CAP
and
V
SS
, using leads and traces that are as short as pos-
sible. As with all high-speed
CMOS
ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK22C48 performs a
READ
cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A
0-10
determines which of
the 2,048 data bytes will be accessed. When the
READ
is initiated by an address transition, the out-
puts will be valid after a delay of t
AVQV
(
READ
cycle
#1). If the
READ
is initiated by E or G, the outputs will
be valid at t
ELQV
or at t
GLQV
, whichever is later (
READ
cycle #2). The data outputs will repeatedly respond
to address changes within the t
AVQV
access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
SRAM WRITE
A
WRITE
cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the
WRITE
cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
0-7
will be written into the memory if it is valid t
DVWH
before the end of a W controlled
WRITE
or t
DVEH
before the end of an E controlled
WRITE
.
It is recommended that G be kept high during the
entire
WRITE
cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CAP
< V
RESET
), an internal
RECALL
request will be
latched. When V
CAP
once again exceeds the sense
voltage of V
SWITCH
, a
RECALL
cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK22C48 is in a
WRITE
state at the end of
power-up
RECALL
, the
SRAM
data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC
or between E and system V
CC
.
AutoStore
OPERATION
The STK22C48 can be powered in one of three
modes.
During
STK22C48 will draw current from V
CCX
to charge a
capacitor connected to the V
CAP
pin. This stored
charge will be used by the chip to perform a single
STORE
operation. After power up, when the voltage
on the V
CAP
pin drops below V
SWITCH
, the part will
automatically disconnect the V
CAP
pin from V
CCX
and
initiate a
STORE
operation.
normal
AutoStore
operation,
the
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68
μ
F and
220
μ
F (
±
20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
CCX
and
V
CAP
are connected to the + 5V power supply without
the 68
μ
F capacitor. In this mode the
AutoStore
function of the STK22C48 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that V
CCX
does not drop below
3.6V during the 10ms
STORE
cycle.
If an automatic
STORE
on power loss is not required,
then V
CCX
can be tied to ground and + 5V applied to
V
CAP
(Figure 4). This is the
AutoStore
Inhibit
mode, in which the
AutoStore
function is disabled.
If the STK22C48 is operated in this configuration,
references to V
CCX
should be changed to V
CAP
throughout this data sheet. In this mode,
STORE
operations may be triggered with the HSB pin. It is
not permissable to change between these three
options “on the fly”.
DEVICE OPERATION
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