參數(shù)資料
型號(hào): STK22C48-S35
英文描述: DIODE TVS 20V 400W BIDIR 5% SMA
中文描述: NVRAM中(EEPROM的基礎(chǔ))
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 110K
代理商: STK22C48-S35
STK22C48
July 1999
3-25
HARDWARE MODE SELECTION
Note n:
HSB
STORE
operation occurs only if an SRAM write has been done since the last nonvolatile cycle. After the
STORE
(if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
I/O state assumes G < V
IL
. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE
STORE
CYCLE
Note o:
(V
CC
= 5.0V
±
10%)
b
,
f
Note p:
Note q:
Note r:
E and G low for output behavior.
E and G low and W high for output behavior.
t
RECOVER
is only applicable after t
STORE
is complete.
HARDWARE
STORE
CYCLE
E
W
HSB
A
12
- A
0
(hex)
MODE
I/O
POWER
NOTES
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
o
L
L
H
X
Write SRAM
Input Data
Active
X
X
L
X
Nonvolatile
STORE
Output High Z
l
CC2
n
NO.
SYMBOLS
PARAMETER
STK22C48
UNITS
NOTES
Standard
Alternate
MIN
MAX
22
t
STORE
t
HLHZ
STORE
Cycle Duration
10
ms
j, p
23
t
DELAY
t
HLQZ
Time Allowed to Complete SRAM Cycle
1
μ
s
j, q
24
t
RECOVER
t
HHQX
Hardware
STORE
High to Inhibit Off
700
ns
p, r
25
t
HLHX
Hardware
STORE
Pulse Width
15
ns
26
t
HLBL
Hardware
STORE
Low to Store Busy
300
ns
DATA VALID
HSB (IN)
DATA VALID
25
t
HLHX
23
t
DELAY
22
t
STORE
24
t
RECOVER
HSB (OUT)
HIGH IMPEDANCE
26
t
HLBL
HIGH IMPEDANCE
DQ (DATA OUT)
相關(guān)PDF資料
PDF描述
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