參數(shù)資料
型號: STK1743
廠商: Electronic Theatre Controls, Inc.
英文描述: NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
中文描述: 內(nèi)華達州時間8K的乘八與實時自動存儲非易失性SRAM -時間時鐘
文件頁數(shù): 9/10頁
文件大?。?/td> 253K
代理商: STK1743
STK1743
March 1999
7-9
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALLcycle
Internally,
RECALL
is a two-step procedure. First,
the
SRAM
data is cleared, and second, the nonvola-
tile information is transferred into the
SRAM
cells.
After the t
RECALL
cycle time the
SRAM
will once again
be ready for
READ
and
WRITE
operations. The
RECALL
operation in no way alters the data in the
EEPROM
cells. The nonvolatile data can be recalled
an unlimited number of times. Note that the
RTC
registers are not affected by nonvolatile operations.
AutoStore
TM
OPERATION
The STK1743 uses capacitance built into the mod-
ule to perform an automatic
STORE
on power down.
In order to prevent unnecessary
STORE
operations,
automatic
STORE
s will be ignored unless at least
one
WRITE
operation has taken place since the
most recent
STORE
or
RECALL
cycle. Software-
initiated
STORE
cycles are performed regardless of
whether a
WRITE
operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC
< V
RESET
), an internal recall request will be
latched. When V
CC
once again exceeds V
SWITCH
, a
RECALL
cycle will automatically be initiated and will
take t
RESTORE
to complete.
HARDWARE PROTECT
The STK1743 offers hardware protection against
inadvertent
STORE
and
SRAM WRITE
operation dur-
ing low-voltage conditions. When V
CC
< V
SWITCH
, all
software
STORE
operations and
SRAM
writes are
inhibited.
LOW AVERAGE ACTIVE POWER
The STK1743 draws significantly less current when
it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
CC
and
READ
cycle
time. Worst-case current consumption is shown for
both
CMOS
and
TTL
input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE
cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK1743 depends on the following items:
1)
CMOS
vs.
TTL
input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
READ
s to
WRITE
s; 5) the operating
temperature; 6) the V
CC
level; and 7) I/O loading.
Figure 2: I
CC
(max) Reads
0
20
40
60
80
100
50
100
Cycle Time (ns)
150
200
TTL
CMOS
A
Figure 3: I
CC
(max) Writes
0
20
40
60
80
100
50
100
Cycle Time (ns)
150
200
TTL
CMOS
A
相關(guān)PDF資料
PDF描述
STK1743-D25 NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
STK1743-D45I NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
STK1743-D25I NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
STK1743-D35 NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
STK1743-D35I NV TIME 8K X 8 AUTOSTORE NVSRAM WITH REAL - TIME CLOCK
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