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參數(shù)資料
| 型號： | STK16C88-3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32K x 8 AutoStorePlus nvSRAM 3.3V QuantumTrap CMOS Nonvolatile Static RAM |
| 中文描述： | 32K的× 8 AutoStorePlus非易失3.3 QuantumTrap的CMOS非易失靜態(tài)RAM |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 114K |
| 代理商： | STK16C88-3 |
STK16C88-3
March 2006
7
Document Control # ML0019 rev 0.2
The
AutoStorePlus
STK16C88-3 is a fast 32K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral
QuantumTrap
Nonvolatile Elements while power is unavailable.
The nonvolatility of the STK16C88-3 does not
require any system intervention or support:
AutoStorePlus
on power-down and automatic
RECALL on power-up guarantee data integrity with-
out the use of batteries.
NOISE CONSIDERATIONS
Note that the STK16C88-3 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1
μ
F connected between V
CC
and V
SS
, using leads and traces that are as short as
possible. As with all high-speed
CMOS
ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK16C88-3 performs a
READ
cycle whenever
E and G are low and W is high. The address speci-
fied on pins A
0-14
determines which of the 32,768
data bytes will be accessed. When the
READ
is initi-
ated by an address transition, the outputs will be
valid after a delay of t
AVQV
(
READ
cycle #1). If the
READ
is initiated by E or G, the outputs will be valid
at t
ELQV
or at t
GLQV
, whichever is later (
READ
cycle #2).
The data outputs will repeatedly respond to address
changes within the t
AVQV
access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A
WRITE
cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
WRITE
cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7
will be writ-
ten into the memory if it is valid t
DVWH
before the end
of a W controlled
WRITE
or t
DVEH
before the end of an
E controlled
WRITE
.
It is recommended that G be kept high during the
entire
WRITE
cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
AutoStorePlus
OPERATION
The STK16C88-3’s automatic
STORE
on power-
down is completely transparent to the system. The
AutoStore
initiation takes less than 500ns when
power is lost (V
CC
< V
SWITCH
) at which point the part
depends only on its internal capacitor for
STORE
completion. If the power supply drops faster than
20
μ
s/volt before Vccx reaches Vswitch, then a 2.2
ohm resistor should be inserted between Vccx and
the system supply to avoid a momentary excess of
current between Vccx and Vcap.
In order to prevent unneeded
STORE
operations,
automatic
STORE
s will be ignored unless at least
one
WRITE
operation has taken place since the
most recent
STORE
or
RECALL
cycle. Software-
initiated
STORE
cycles are performed regardless of
whether or not a
WRITE
operation has taken place.
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CC
< V
RESET
), an internal
RECALL
request will be
latched. When V
CC
once again exceeds the sense
voltage of V
SWITCH
, a
RECALL
cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK16C88-3 is in a
WRITE
state at the end of
power-up
RECALL
, the
SRAM
data will be corrupted.
To help avoid this situation, a 10k
Ω
resistor should
be connected either between W and system V
CC
or
between E and system V
CC
.
SOFTWARE NONVOLATILE
STORE
The STK16C88-3 software
STORE
cycle is initiated
by executing sequential
READ
cycles from six spe-
cific address locations. During the
STORE
cycle an
erase of the previous nonvolatile data is first per-
formed, followed by a program of the nonvolatile
elements. The program operation copies the
SRAM
data into nonvolatile memory. Once a
STORE
cycle
is initiated, further input and output are disabled until
the cycle is completed.
Because a sequence of
READ
s from specific
addresses is used for
STORE
initiation, it is impor-
tant that no other
READ
or
WRITE
accesses inter-
vene in the sequence or the sequence will be
aborted and no
STORE
or
RECALL
will take place.
DEVICE OPERATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STK16C88-3WF35 | 32K x 8 AutoStorePlus nvSRAM 3.3V QuantumTrap CMOS Nonvolatile Static RAM |
| STK16C88-3WF35I | 32K x 8 AutoStorePlus nvSRAM 3.3V QuantumTrap CMOS Nonvolatile Static RAM |
| STK16C88 | 32K x 8 AutoStorePlus⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM |
| STK16C88-25 | 32K x 8 AutoStorePlus⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM |
| STK16C88-35 | 32K x 8 AutoStorePlus⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STK16C88-3WF35 | 功能描述:NVRAM 32Kbx8 3.0-3.6V AutoStorePlus RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK16C88-3WF35I | 功能描述:NVRAM 32Kbx8 3.0-3.6V AutoStorePlus RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK16C88-3WF35ITR | 制造商:Cypress Semiconductor 功能描述:STK16C88-3WF35ITR - Tape and Reel |
| STK16C88-3WF35TR | 制造商:Cypress Semiconductor 功能描述:STK16C88-3WF35TR - Tape and Reel |
| STK16C88-WF25 | 功能描述:NVRAM 32Kbx8 4.5-5.5V AutoStorePlus RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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