參數(shù)資料
型號(hào): STK16C68-S20I
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 8K x 8 AutoStorePlus⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM
中文描述: 8K的× 8 AutoStorePlus⑩⑩非易失QuantumTrap的CMOS非易失性靜態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù): 3/9頁(yè)
文件大?。?/td> 99K
代理商: STK16C68-S20I
STK16C68
July 1999
4-75
SRAM READ CYCLES #1 & #2
(V
CC
= 5.0V
±
10%)
b
Note g:
Note h:
Note i:
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
g, h
SRAM READ CYCLE #2:
E
Controlled
g
NO.
SYMBOLS
PARAMETER
STK16C68-20
STK16C68-25
STK16C68-35
STK16C68-45
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
t
ELQV
t
AVAV
g
t
AVQV
h
t
ACS
Chip Enable Access Time
20
25
35
45
ns
2
t
RC
Read Cycle Time
20
25
35
45
ns
3
t
AA
Address Access Time
22
25
35
45
ns
4
t
GLQV
t
AXQX
h
t
OE
Output Enable to Data Valid
8
10
15
20
ns
5
t
OH
Output Hold after Address Change
5
5
5
5
ns
6
t
ELQX
t
EHQZ
i
t
LZ
Chip Enable to Output Active
5
5
5
5
ns
7
t
HZ
Chip Disable to Output Inactive
7
10
13
15
ns
8
t
GLQX
t
GHQZ
i
t
ELICCH
f
t
EHICCL
e, f
t
OLZ
Output Enable to Output Active
0
0
0
0
ns
9
t
OHZ
Output Disable to Output Inactive
7
10
13
15
ns
10
t
PA
Chip Enable to Power Active
0
0
0
0
ns
11
t
PS
Chip Disable to Power Standby
25
25
35
45
ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
8
t
GLQX
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
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STK16C68-W20I 8K x 8 AutoStorePlus⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM
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