- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄231009 > STK15C88-3W35 32K X 8 NON-VOLATILE SRAM, 35 ns, PDIP28 PDF資料下載
參數(shù)資料
| 型號： | STK15C88-3W35 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 NON-VOLATILE SRAM, 35 ns, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 291K |
| 代理商： | STK15C88-3W35 |
STK15C88-3
September 2002
7
The STK15C88-3 is a versatile memory chip that
provides
several
modes
of
operation.
The
STK15C88-3 can operate as a standard 32K x 8
SRAM
. It has a 32K x 8 EEPROM shadow to which
the SRAM information can be copied, or from which
the SRAM can be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK15C88-3 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1
F connected between V
CC
and V
SS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK15C88-3 performs a READ cycle whenever
E and G are low and W is high. The address speci-
fied on pins A
0-14 determines which of the 32,768
data bytes will be accessed. When the READ is initi-
ated by an address transition, the outputs will be
valid after a delay of t
AVQV (READ cycle #1). If the
READ
is initiated by E or G, the outputs will be valid
at t
ELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the t
AVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7 will be writ-
ten into the memory if it is valid t
DVWH before the end
of a W controlled WRITE or t
DVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ after W goes low.
SOFTWARE NONVOLATILE STORE
The STK15C88-3 software STORE cycle is initiated
by executing sequential READ cycles from six spe-
cific address locations. During the STORE cycle an
erase of the previous nonvolatile data is first per-
formed, followed by a program of the nonvolatile
elements. The program operation copies the SRAM
data into nonvolatile memory. Once a STORE cycle
is initiated, further input and output are disabled until
the cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ
sequence must be performed:
1. Read address
0E38 (hex)
Valid READ
2. Read address
31C7 (hex)
Valid READ
3. Read address
03E0 (hex)
Valid READ
4. Read address
3C1F (hex)
Valid READ
5. Read address
303F (hex)
Valid READ
6. Read address
0FC0 (hex)
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
STORE cycle time has
been fulfilled, the SRAM will again be activated for
READ
and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
1. Read address
0E38 (hex)
Valid READ
2. Read address
31C7 (hex)
Valid READ
3. Read address
03E0 (hex)
Valid READ
4. Read address
3C1F (hex)
Valid READ
5. Read address
303F (hex)
Valid READ
6. Read address
0C63 (hex)
Initiate RECALL cycle
DEVICE OPERATION
相關PDF資料 |
PDF描述 |
|---|---|
| SYS32256LKI-020 | 256K X 32 MULTI DEVICE SRAM MODULE, 20 ns, SMA64 |
| S29CL032J0PFAM020 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J0RQAM013 | 1M X 32 FLASH 3.3V PROM, 48 ns, PQFP80 |
| S71PL032J80BAW052 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71PL032J80BAW074 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| STK15C88-N35I | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| STK15C88-NF25 | 功能描述:NVRAM 32Kbx8 4.5-5.5V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK15C88-NF25I | 功能描述:NVRAM 32Kbx8 4.5-5.5V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK15C88-NF25ITR | 功能描述:NVRAM 32Kbx8 4.5-5.5V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK15C88-NF25TR | 功能描述:NVRAM 32Kbx8 4.5-5.5V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。