參數(shù)資料
型號(hào): STK14C88-W35M
元件分類: SRAM
英文描述: 32K X 8 NON-VOLATILE SRAM, 35 ns, PDIP32
封裝: 0.600 INCH, PLASTIC, DIP-32
文件頁(yè)數(shù): 1/13頁(yè)
文件大?。?/td> 387K
代理商: STK14C88-W35M
September 2003
1
Document Control # ML0014 rev 0.1
PIN CONFIGURATIONS
VCAP
A14
A12
A7
A6
A5
A4
A3
NC
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCCX
HSB
A13
A8
A9
A11
G
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32 - LCC
32 - DIP
32 - SOIC
PIN NAMES
A0 - A14
Address Inputs
DQ0 -DQ7
Data In/Out
E
Chip Enable
W
Write Enable
G
Output Enable
HSB
Hardware Store Busy (I/O)
VCCX
Power (+ 5V)
VCAP
Capacitor
VSS
Ground
STK14C88
32K x 8 AutoStorenvSRAM
QuantumTrap CMOS
Nonvolatile Static RAM
FEATURES
25ns, 35ns and 45ns Access Times
“Hands-off” Automatic STORE with External
68
F Capacitor on Power Down
STORE to nonvolatile elements Initiated by
Hardware, Software or AutoStore
RECALL to SRAM Initiated by Software or
Power Restore
10mA Typical I
CC at 200ns Cycle Time
Unlimited READ, WRITE and RECALL Cycles
1,000,000 STORE Cycles to nonvolatile ele-
ments (Commercial/Industrial)
100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
Single 5V + 10% Operation
Commercial, Industrial and Military Tempera-
tures
32-Pin SOIC, DIP and LCC Packages
DESCRIPTION
The Simtek STK14C88 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in the nonvolatile elements.
Data transfers from the SRAM to the nonvolatile ele-
ments (the STORE operation) can take place auto-
matically on power down. A 68
F or larger capacitor
tied from V
CAP to ground guarantees the STORE
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the nonvolatile elements to the SRAM (the RECALL
operation) take place automatically on restoration of
power. Initiation of STORE and RECALL cycles can
also be software controlled by entering specific read
sequences. A hardware STORE may be initiated with
the HSB pin.
BLOCK DIAGRAM
A0 A1 A2 A3 A4 A10
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW
DE
CODE
R
INPU
T
B
U
FFERS
Quantum Trap
512 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SOFTWARE
DETECT
G
E
W
HSB
VCCX
VCAP
A0 - A13
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