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參數(shù)資料
| 型號： | STK14C88-3RF35 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32K x 8 AutoStore⑩ nvSRAM QuantumTrap CMOS Nonvolatile StaticRAM |
| 中文描述： | 32K的× 8自動存儲⑩非易失QuantumTrap的CMOS非易失StaticRAM |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 371K |
| 代理商： | STK14C88-3RF35 |
STK14C88-3
November 2003
8
Document Control # ML0015 rev 0.3
The STK14C88-3 has two separate modes of opera-
tion:
SRAM
mode and nonvolatile mode. In
SRAM
mode, the memory operates as a standard fast
static
RAM
. In nonvolatile mode, data is transferred
from
SRAM
to nonvolatile elements (the
STORE
operation) or from nonvolatile elements to
SRAM
(the
RECALL
operation). In this mode
SRAM
func-
tions are disabled.
NOISE CONSIDERATIONS
The STK14C88-3 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1
μ
F connected between V
CAP
and
V
SS
, using leads and traces that are as short as pos-
sible. As with all high-speed
CMOS
ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88-3 performs a
READ
cycle whenever
E and G are low and W and HSB are high. The
address specified on pins A
0-14
determines which of
the 32,768 data bytes will be accessed. When the
READ
is initiated by an address transition, the out-
puts will be valid after a delay of t
AVQV
(
READ
cycle
#1). If the
READ
is initiated by E or G, the outputs will
be valid at t
ELQV
or at t
GLQV
, whichever is later (
READ
cycle #2). The data outputs will repeatedly respond
to address changes within the t
AVQV
access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
SRAM WRITE
A
WRITE
cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the
WRITE
cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
0-7
will be written into the memory if it is valid t
DVWH
before the end of a W controlled
WRITE
or t
DVEH
before the end of an E controlled
WRITE
.
It is recommended that G be kept high during the
entire
WRITE
cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CAP
< V
RESET
), an internal
RECALL
request will be
latched. When V
CAP
once again exceeds the sense
voltage of V
SWITCH
, a
RECALL
cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK14C88-3 is in a
WRITE
state at the end of
power-up
RECALL
, the
SRAM
data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC
or between E and system V
CC
.
SOFTWARE NONVOLATILE
STORE
The STK14C88-3 software
STORE
cycle is initiated
by executing sequential
E
controlled
READ
cycles
from six specific address locations. During the
STORE
cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. The program operation copies
the
SRAM
data into nonvolatile memory. Once a
STORE
cycle is initiated, further input and output are
disabled until the cycle is completed.
Because a sequence of
READ
s from specific
addresses is used for
STORE
initiation, it is impor-
tant that no other
READ
or
WRITE
accesses inter-
vene in the sequence, or the sequence will be
aborted and no
STORE
or
RECALL
will take place.
To initiate the software
STORE
cycle, the following
READ
sequence must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate
STORE
cycle
The software sequence must be clocked with E con-
trolled
READ
s.
Once the sixth address in the sequence has been
entered, the
STORE
cycle will commence and the
chip will be disabled. It is important that
READ
cycles
and not
WRITE
cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
STORE
cycle time has
been fulfilled, the
SRAM
will again be activated for
READ
and
WRITE
operation.
DEVICE OPERATION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STK14C88-3WF35 | 功能描述:NVRAM 32Kbx8 3.0-3.6V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK14C88-3WF35I | 功能描述:NVRAM 32Kbx8 3.0-3.6V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK14C88-3WF35ITR | 制造商:Cypress Semiconductor 功能描述:STK14C88-3WF35ITR - Tape and Reel |
| STK14C88-3WF35TR | 制造商:Cypress Semiconductor 功能描述:STK14C88-3WF35TR - Tape and Reel |
| STK14C88-3WF45 | 功能描述:NVRAM 32Kbx8 3.0-3.6V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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