參數(shù)資料
型號: STK14C88-3RF35
元件分類: SRAM
英文描述: 32K X 8 NON-VOLATILE SRAM, 35 ns, PDSO48
封裝: 0.300 INCH, PLASTIC, SSOP-48
文件頁數(shù): 1/13頁
文件大?。?/td> 371K
代理商: STK14C88-3RF35
November 2003
1
Document Control # ML0015 rev 0.3
PIN CONFIGURATIONS
32 - DIP
32 - SOIC
48 - SSOP
VCAP
A14
A12
A7
A6
A5
A4
A3
NC
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCCX
HSB
A13
A8
A9
A11
G
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(not to scale)
PIN NAMES
A0 - A14
DQ0 -DQ7
E
W
G
HSB
VCCX
VCAP
VSS
Address
Inputs
Data In/Out
Chip
Enable
Write
Enable
Output
Enable
Hardware
Store
Busy (I/O)
Power
(+ 3.3V)
Capacitor
Ground
STK14C88-3
32K x 8 AutoStorenvSRAM
QuantumTrap CMOS
Nonvolatile Static RAM
FEATURES
35ns, 45ns and 55ns Access Times
“Hands-off” Automatic STORE with External
68
F Capacitor on Power Down
STORE to nonvolatile elements Initiated by
Hardware, Software or AutoStore
RECALL to SRAM Initiated by Software or
Power Restore
10mA Typical I
CC at 200ns Cycle Time
Unlimited READ, WRITE and RECALL Cycles
1,000,000 STORE Cycles to nonvolatile ele-
ments (Commercial/Industrial)
100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
Single 3.3V + 0.3V Operation
Commercial and Industrial Temperatures
32-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK14C88-3 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in nonvolatile elements. Data
transfers from the SRAM to the nonvolatile elements
(the STORE operation) can take place automatically
on power down. A 68
F or larger capacitor tied from
V
CAP to ground guarantees the STORE operation,
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the nonvolatile
elements to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initia-
tion of STORE and RECALL cycles can also be soft-
ware
controlled
by
entering
specific
read
sequences. A hardware STORE may be initiated with
the HSB pin.
BLOCK DIAGRAM
A0 A1 A2 A3 A4 A10
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
R
O
W
DE
CO
DE
R
IN
PU
T
BUF
F
ER
S
Quantum Trap
512 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SOFTWARE
DETECT
G
E
W
HSB
VCCX
VCAP
A0 - A13
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