- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373508 > STK12C68-M (Electronic Theatre Controls, Inc.) CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM PDF資料下載
參數(shù)資料
| 型號： | STK12C68-M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM |
| 中文描述： | 的CMOS非易失SRAM 8K的乘八自動存儲非易失靜態(tài)RAM |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 72K |
| 代理商： | STK12C68-M |
STK12C68-M
4-59
address locations. By relying on
READ
cycles only, the
STK12C68-M implements nonvolatile operation while
remaining compatible with standard 8Kx8 SRAMs.
During the
STORE
cycle, an erase of the previous
nonvolatile data is first performed, followed by a pro-
gram of the nonvolatile elements. The program opera-
tion copies the
SRAM
data into the nonvolatile ele-
ments. Once a
STORE
cycle is initiated, further input
and output are disabled until the cycle is completed.
Because a sequence of addresses is used for
STORE
initiation, it is critical that no other read or write ac-
cesses intervene in the sequence or the sequence will
be aborted.
To initiate the
STORE
cycle the following
READ
se-
quence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE Cycle
Once the sixth address in the sequence has been
entered, the
STORE
cycle will commence and the chip
will be disabled. It is important that
READ
cycles and
not
WRITE
cycles be used in the sequence, although it
is not necessary that G be
LOW
for the sequence to be
valid. After the t
STORE
cycle time has been fulfilled, the
SRAM
will again be activated for
READ
and
WRITE
operation.
SOFTWARE RECALL
A
RECALL
cycle of the
EEPROM
data into the
SRAM
is
initiated with a sequence of
READ
operations in a
manner similar to the
STORE
initiation. To initiate the
RECALL
cycle the following sequence of
READ
opera-
tions must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000(hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
Internally,
RECALL
is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the
SRAM
cells. The
RECALL
operation in no way alters the data in the
DEVICE OPERATION
The STK12C68-M has two separate modes of opera-
tion:
SRAM
mode and nonvolatile mode. In
SRAM
mode, the memory operates as a standard fast static
RAM
. In nonvolatile mode, data is transferred from
SRAM
to
EEPROM
(the
STORE
operation) or from
EEPROM
to
SRAM
(the
RECALL
operation). In this mode
SRAM
functions are disabled.
STORE
cycles may be initiated under user control via a
software sequence or HSB assertion and are also
automatically initiated when the power supply voltage
level of the chip falls below V
SWITCH
.
RECALL
opera-
tions are automatically initiated upon power-up and
whenever the power supply voltage level rises above
V
SWITCH
.
RECALL
cycles may also be initiated by a
software sequence.
SRAM READ
The STK12C68-M performs a
READ
cycle whenever E
and G are
LOW
and HSB and W are
HIGH
. The address
specified on pins A
0-12
determines which of the 8192
data bytes will be accessed. When the
READ
is initiated
by an address transition, the outputs will be valid after
a delay of t
AVQV
. If the
READ
is initiated by E or G, the
outputs will be valid at t
ELQV
or at t
GLQV
, whichever is
later. The data outputs will repeatedly respond to
address changes within the t
AVQV
access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought
HIGH
or W or HSB is brought
LOW
.
SRAM WRITE
A write cycle is performed whenever E and W are
LOW
and HSB is high
. The address inputs must be stable prior
to entering the
WRITE
cycle and must remain stable
until either E or W go
HIGH
at the end of the cycle. The
data on pins DQ
0-7
will be written into the memory if it
is valid t
DVWH
before the end of a W controlled
WRITE
or t
DVEH
before the end of an E controlled
WRITE
.
It is recommended that G be kept
HIGH
during the entire
WRITE
cycle to avoid data bus contention on the
common I/O lines. If G is left
LOW
, internal circuitry will
turn off the output buffers t
WLQZ
after W goes
LOW
.
SOFTWARE STORE
The STK12C68-M software
STORE
cycle is initiated by
executing sequential
READ
cycles from six specific
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STK12C68-5K40M | Ground Cord; Features:Tough vinyl cord and strain relief provide long life; 15' cord.; 3/8? stud (male) for mat conn..;#10 ring terminal for ground conn.; Terminal Type:Ring RoHS Compliant: NA |
| STK14C88-5C35M | 32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK14C88-5C45M | 32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK14C88-5K35M | 32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK14C88-5K45M | 32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STK12C68-PF25 | 功能描述:NVRAM 8Kbx8 4.5-5.5V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK12C68-PF25I | 功能描述:NVRAM 8Kbx8 4.5-5.5V AutoStore RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| STK12C68-PF25ITR | 制造商:Cypress Semiconductor 功能描述:STK12C68-PF25ITR - Tape and Reel |
| STK12C68-PF25TR | 制造商:Cypress Semiconductor 功能描述:STK12C68-PF25TR - Tape and Reel |
| STK12C68-PF45 | 功能描述:NVRAM 64 Kbit (8K x 8) NVSRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。