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參數(shù)資料
| 型號： | STK11C88-3S45 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| 中文描述： | 32K的× 8非易失性SRAM 3.3伏量子端粒酶的CMOS非易失靜態(tài)RAM |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 90K |
| 代理商： | STK11C88-3S45 |
STK11C88-3
July 1999
5-17
The STK11C88-3 is a versatile 3.3V V
CC
memory
chip that provides several modes of operation. The
STK11C88-3 can operate as a standard 32K x 8
SRAM
. It has a 32K x 8
EEPROM
shadow to which
the
SRAM
information can be copied or from which
the
SRAM
can be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C88-3 is a high-speed memory
and so must have a high frequency bypass capaci-
tor of approximately 0.1
μ
F connected between V
CC
and V
SS
, using leads and traces that are as short as
possible. As with all high-speed
CMOS
ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK11C88-3 performs a
READ
cycle whenever
E and G are low and W is high. The address speci-
fied on pins A
0-14
determines which of the 32,768
data bytes will be accessed. When the
READ
is initi-
ated by an address transition, the outputs will be
valid after a delay of t
AVQV
(
READ
cycle #1). If the
READ
is initiated by E or G, the outputs will be valid
at t
ELQV
or at t
GLQV
, whichever is later (
READ
cycle #2).
The data outputs will repeatedly respond to address
changes within the t
AVQV
access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A
WRITE
cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
WRITE
cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7
will be writ-
ten into the memory if it is valid t
DVWH
before the end
of a W controlled
WRITE
or t
DVEH
before the end of an
E controlled
WRITE
.
It is recommended that G be kept high during the
entire
WRITE
cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
SOFTWARE NONVOLATILE
STORE
The STK11C88-3 software
STORE
cycle is initiated
by executing sequential
READ
cycles from six spe-
cific address locations. During the
STORE
cycle an
erase of the previous nonvolatile data is first per-
formed, followed by a program of the nonvolatile
elements. The program operation copies the
SRAM
data into nonvolatile memory. Once a
STORE
cycle
is initiated, further input and output are disabled until
the cycle is completed.
Because a sequence of reads from specific
addresses is used for
STORE
initiation, it is impor-
tant that no other
READ
or
WRITE
accesses inter-
vene in the sequence, or the sequence will be
aborted and no
STORE
or
RECALL
will take place.
To initiate the software
STORE
cycle, the following
READ
sequence must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate
STORE
cycle
The software sequence is clocked with E controlled
READ
s.
Once the sixth address in the sequence has been
entered, the
STORE
cycle will commence and the
chip will be disabled. It is important that
READ
cycles
and not
WRITE
cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
STORE
cycle time has
been fulfilled, the
SRAM
will again be activated for
READ
and
WRITE
operation.
SOFTWARE NONVOLATILE
RECALL
A software
RECALL
cycle is initiated with a sequence
of
READ
operations in a manner similar to the soft-
ware
STORE
initiation. To initiate the
RECALL
cycle,
the following sequence of
READ
operations must be
performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate
RECALL
cycle
DEVICE OPERATION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| STK11C88-3S45I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK11C88-3S55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK11C88-3S55I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK11C88-3SF25 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:32K x 8 nvSRAM 3.3V QuantumTrap⑩ CMOS Nonvolatile Static RAM |
| STK11C88-3SF25I | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:32K x 8 nvSRAM 3.3V QuantumTrap⑩ CMOS Nonvolatile Static RAM |
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