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          • 您現(xiàn)在的位置:買(mǎi)賣(mài)IC網(wǎng) > PDF目錄372330 > STEL-1377Q FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC PDF資料下載
          參數(shù)資料
          型號(hào): STEL-1377Q
          英文描述: FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC
          中文描述: 頻率合成器|雙酯| 64管腳|塑料
          文件頁(yè)數(shù): 17/19頁(yè)
          文件大?。?/td> 284K
          代理商: STEL-1377Q
          第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)
          17
          STEL-2060C
          Input
          Initial State
          Alternate States
          1
          2
          G1
          G1
          n
          G2
          n
          * G2
          n+1
          G2
          n
          * G2
          n+1
          G1
          n+2
          G2
          n+1
          G1
          n+2
          G2
          n+2
          *
          (No delay)
          (One symbol
          delay)
          (Two symbol
          delay)
          PARL
          Input
          Initial State
          Alternate State
          0
          G1
          G1
          n
          N.A.
          G2
          n
          G2
          n
          N.A.
          G1
          n+1
          G2
          1
          G1
          G1
          n
          G2
          n
          G2
          n
          G1
          n
          G2
          Input
          Initial State
          Alternate States
          3
          1
          2
          4
          5
          G1
          G1
          n
          G2
          n+1
          G2
          n+2
          *
          G2
          n
          * G1
          n+2
          G2
          n+3
          (No Invert/Swap (Invert/Swap
          No delay)
          G2
          n
          * G1
          n+2
          G2
          n+3
          G1
          n
          G2
          n+1
          G2
          n+2
          * G2
          n+1
          G2
          n+2
          * G1
          n+4
          G2
          n
          * G1
          n+2
          G2
          n+3
          G2
          n+1
          G2
          n+2
          * G1
          n+4
          G2
          n
          * G1
          n+2
          G2
          n+3
          (Invert/Swap
          One symb. delay)
          *G2
          n+1
          G2
          n+2
          *G1
          n+4
          G1
          n+2
          G2
          n+3
          G2
          n+4
          (No Invert/Swap
          Two symb. delay)
          G1
          n+2
          G2
          n+3
          G2
          n+4
          *
          G2
          n+1
          G2
          n+2
          *G1
          n+4
          (Invert/Swap
          Two symb. delay)
          G2
          (No Invert/Swap
          One symb. delay)
          No delay)
          3. RATE
          2
          /
          3
          , PARL = 1 (QPSK MODE)
          NODE SYNC SEQUENCES
          1. RATE
          1
          /
          2
          2. RATE
          2
          /
          3
          , PARL = 0 (BPSK MODE)
          BER PERFORMANCE
          The coding gain obtained by the use of Convolutional coding
          and Viterbi decoding is extremely dependent on many
          parameters. Not surprisingly, the code rate is a primary
          factor, but so are the bit error rate (BER) and amplitude of the
          input signal. The BER affects the coding gain because the
          error correction capability of the Viterbi decoder is
          dependent on the statistics of the errors, specifically the
          clustering of errors. As the BER of the input signal increases,
          so does the clustering, causing a reduction in the error
          correcting capability of the device, along with the coding
          gain. The signal amplitude is important because of the
          weighting given to the signal amplitude as an indication of
          the likelihood of an error in a given symbol pair.
          E
          b
          /N
          o
          BER
          10
          –2
          10
          –3
          10
          –4
          10
          –5
          10
          –6
          10
          –7
          R =
          1
          /
          2
          R =
          2
          /
          3
          R =
          3
          /
          4
          R =
          7
          /
          8
          10
          9
          8
          7
          6
          5
          4
          3
          2
          Uncoded
          10
          –1
          11
          Consequently it is important to maintain the signal
          amplitude at an optimum level in order to maximize the
          performance. The performance curves shown above were
          measured using a digital link simulator with the signal level
          set at one half of full scale; i.e., the signal amplitude without
          noise ranged from 101 to 001 in signed magnitude format, or
          101 to 010 in offset binary format. The coding gain under
          these conditions is about 0.2 dB less than that under
          optimum signal level conditions. The performance of the
          STEL-2060C is shown here for unpunctured operation
          (Rate
          1
          /
          2
          ) as well as punctured operation at the rates for
          which internal depuncturing is supported (Rates
          2
          /
          3
          ,
          3
          /
          4
          and
          7
          /
          8
          ). The error rate for uncoded data is shown for
          comparison.
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          相關(guān)PDF資料
          PDF描述
          STEL-1377S FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC
          STEL-1378A FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC
          STEPHY1 Semiconductor Fuse; Current Rating:35A; Voltage Rating:250V; Fuse Type:Fast Acting; Fuse Terminals:Blade; Diameter:20.6mm; Length:81mm; Series:L25S; Voltage Rating:250V
          STF201-22.TC Semiconductor Fuse; Current Rating:50A; Voltage Rating:250V; Fuse Type:Fast Acting; Fuse Terminals:Blade; Diameter:20.6mm; Length:81mm; Series:L25S; Voltage Rating:250V
          STF201-30.TC Triac; Thyristor Type:Sensitive Gate; Peak Repetitive Off-State Voltage, Vdrm:200V; On-State RMS Current, IT(rms):800mA; Gate Trigger Current (QI), Igt:5mA; Current, It av:0.8A; Leaded Process Compatible:Yes RoHS Compliant: Yes
          相關(guān)代理商/技術(shù)參數(shù)
          參數(shù)描述
          STEL-1377S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC
          STEL-1378A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC
          STEL-2000A+20/CR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC
          STEL-2000A+45/CR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC
          STEL2020 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Convolutional-FEC-Viterbi Error Circuit - Burst and continuous modes
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