參數(shù)資料
型號(hào)： STCD23300F35F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘及定時(shí)
英文描述： 2330 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA12
封裝： 1.20 X 1.60 MM, 0.40 MM PITCH, ROHS COMPLIANT, FLIP CHIP-12
文件頁(yè)數(shù)： 22/39頁(yè)
文件大?。?/td> 1948K
代理商： STCD23300F35F
STCD22x0, STCD23x0, STCD24x0
DC and AC parameters
Doc ID 15400 Rev 2
PSRR
Power supply rejection ratio(3)(4)
VCC = 2.5 V to 5.1 V,
Fripple = 217 Hz,
ILOAD = 20 mA
60
67
dB
VCC = 2.5 V to 5.1 V,
Fripple = 1 kHz,
ILOAD = 20 mA
40
60
VCC = 2.5 V to 5.1 V,
Fripple = 1 MHz,
ILOAD = 20 mA
40
VCC = 2.5 V to 5.1 V,
Fripple = 3.25 MHz,
ILOAD = 20 mA
40
eN
Output noise voltage(3)
ILOAD = 5 mA, 10 Hz to
100 kHz
45
Vrms
tST
Startup time(3)
VTCXO > 90%,
ILOAD = 10 A to 20 mA
150
400
s
tF
Output voltage falling time(3)
VTCXO < 10%,
ILOAD = 0
120
400
s
Clock distribution
fMCLK
Master clock (from external clock
source)
Square wave / sine
wave
10
26
52
MHz
fCLK duty cycle
40
50
60
%
VIN
Input clock voltage level(5)
Square wave
0.8
1.8
VTCXO + 0.2
Vpp
Sine wave
0.8
1
VTCXO + 0.2
Vpp
VOH
Output high
CL = 20 pF
VTCXO – 0.05 VTCXO
V
VOL
Output low
CL = 20 pF
0.05
V
Tr/f
Rise/fall time(6)
CL =10 pF~ 40 pF
1
2
5
ns
IQC
Quiescent current(7)
(including LDO)
1 channel enabled
80
200
A
2 channels enabled
80
200
3 channels enabled
80
200
4 channels enabled
80
200
ICC
Active current(8)
1 channel enabled
1.9
mA
2 channels enabled
3.0
3 channels enabled
4.1
4 channels enabled
5.2
ISB
Standby current
(including LDO)
All buffers off
0.2
1
A
RIN
Input impedance
> 100
k
Ω
Table 10.
DC and AC characteristics (continued)
Sym.
Parameter
Condition(1)
Min
Typ
Max
Unit
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