參數(shù)資料
型號(hào)： STAC9708T
廠商： Electronic Theatre Controls, Inc.
元件分類： Codec
英文描述： Multi-Channel AC97 Codec With Multi-Codec Option
中文描述： 多聲道AC97編解碼器與多編解碼器方案
文件頁(yè)數(shù)： 15/56頁(yè)
文件大?。?/td> 247K
代理商： STAC9708T
SigmaTel, Inc.
Preliminary
STAC9708/11
15
10/02/98
Figure 5
. AC'97 Standard Bi-directional Audio Frame
3.1.1 AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting the
STAC9708/11
DAC inputs, and control registers. Each audio output frame supports up to
12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used
for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one slot time of valid data. The next 12 bit positions sampled by the
STAC9708/11
indicate
which of the corresponding 12 times slots contain valid data. In this way data streams of differing
sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate. The following
diagram illustrates the time slot based AC-Link protocol.
Figure 6
. AC-Link Audio Output Frame
SYNC
BIT_CLK
SDATA_OUT
valid
Frame
slot1
slot2
End of previous audio frame
slot(12) "0"
19
"0"
"0"
"0"
19
19
19
"0"
Data Phase
20.8 uS (48 kHZ)
Tag Phase
12.288 MHz
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
CID1
CID0
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the
STAC9708/11
samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller
transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is
presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the
STAC9708/11
on
OUTGOING STREAMS
INCOMING STREAMS
SYNC
TAG PHASE
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RT
NA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
NA
NA
PCM
LEFT
PCM
RT
STATUS
DATA
STATUS
ADR
TAG
DATA PHASE
PCM
CTR
PCM
LSURR
PCM
RSURR
PCM
LFE
PCM
LALT
PCM
RALT
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