參數(shù)資料
型號: STA013T
廠商: 意法半導(dǎo)體
元件分類: 通用總線功能
英文描述: MPEG 2.5 LAYER III AUDIO DECODER
中文描述: 2.5第三層的MPEG音頻解碼器
文件頁數(shù): 15/38頁
文件大?。?/td> 300K
代理商: STA013T
DATA_REQ_ENABLE
Address: 0x18
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
X
LSB
b0
X
X
b6
X
X
b5
X
X
b4
X
X
b3
X
X
b2
0
1
b1
X
X
Description
buffered output clock
request signal
MUTE
Address: 0x14
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
LSB
b0
0
1
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
CMD_INTERRUPT
Address: 0x16
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
LSB
b0
0
1
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
X = don’t care;
0 = normal operation;
1 = write into I
2
C/Ancillary Data
The INTERRUPT is used to give STA013 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x59 ... 0x5D). Every time the
Master has to extract the new buffer content (5
bytes) it writes into this register, setting it to a
non-zero value.
SYNCSTATUS
Address: 0x40
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
LSB
b0
SS0
0
1
0
1
b6
X
b5
X
b4
X
b3
X
b2
X
b1
SS1
0
0
1
1
Description
Research of sync word
Wait for Confirmation
Synchronised
not used
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
mode.
The buffered Output Clock has the same fre-
quency than the input clock (XTI)
STA013 - STA013B - STA013T
15/38
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