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| 型號： | STA-6033 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Product Description |
| 中文描述： | 產(chǎn)品描述 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 264K |
| 代理商： | STA-6033 |
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-103643 Rev B
Preliminary
STA-6033 4.9-5.9 GHz Power Amp
Pin Out Description
Pin #
Function
Description
1,4,9,12,13
N/C
Pins are not used. May be grounded, left open, or connected to adjacent pin.
5
VPC1
VPC1 is the bias control pin for the stage 1 active bias circuit. An external series resistor is required for proper
setting of bias levels. Refer to the evaluation board schematic for resistor value.
To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 16
(Vbias) unless Vpc supply current capability is less than 10 mA.
6
VPC2
VPC2 is the bias control pin for the stage 2 active bias circuit. An external series resistor is required for proper
setting of bias levels. Refer to the evaluation board schematic for resistor value.
To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 16
(Vbias) unless Vpc supply current capability is less than 10 mA.
7
VPC3
VPC3 is the control pin for the stage 3 active bias circuits. An external series resistor is required for proper set-
ting of bias levels. Refer to the evaluation board schematic for resistor value.
To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 16
(Vbias) unless Vpc supply current capability is less than 10 mA.
8
Vdet
Ouput power detector voltage. Load with 10K-100K ohms to ground for best performance.
2,3
RFIN
RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be
used for proper operation.
10,11
RFOUT
RF output pin. This is also another connection to the 3rd stage collector
14
VC3
3rd stage collector bias pin. Apply 3.0V to 3.6V to this pin.
15
VC2
2nd stage collector bias pin. Apply 3.0V to 3.6V to this pin.
16
VC1,Vbias
1st stage collector bias pin and active bias network VCC. Apply 3.0V to 3.6V to this pin.
EPAD
Gnd
Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for
optimum thermal and RF performance. Several vias should be located under the EPAD as shown in the rec-
ommended land pattern (page 5).
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Absolute Maximum Ratings
Parameters
Value
Unit
VC3 Collector Bias Current (pin16)
400
mA
VC2 Collector Bias Current (pin18)
140
mA
VC1 Collector Bias Current (pin19)
50
mA
Device Voltage (V
D
)
Power Dissipation
4.5
V
1.4
W
Operating Lead Temperature (T
L
)
RF Input Power for 50 ohm load
-40 to +85
oC
20
dBm
Storage Temperature Range
-40 to +150
oC
Operating Junction Temperature (T
J
)
ESD Human Body Model
+150
oC
>1000
V
Operation of this device beyond any one of these limits may
cause permanent damage. For reliable continuous operation
the device voltage and current must not exceed the maximum
operating values specified in the table on page one.
Bias conditions should also satisfy the following expression:
I
D
V
D
< (T
J
- T
L
) / R
TH’
j-l
Simplified Device Schematic
Stage 1
Bias
Stage 2
Bias
Stage 3
Bias
Pin 2, 3
Pin 10,11
Pin
5
Pin
16
Pin
6
Pin
15
Pin
7
Pin
14
Pin
8
EPAD
EPAD
EPAD
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