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參數(shù)資料
| 型號： | ST93C57C |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 107K |
| 代理商： | ST93C57C |
EraseAll
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ’1’). A dummy
addressis input duringthe instructiontransfer and
the erase is made in the sameway as the ERASE
instruction. If the ST93C56 is still performing the
erasecycle,theBusysignal(Q=0) willbereturned
if S isdriven high,andthe ST93C56will ignoreany
data on the bus. When the erase cycle is com-
pleted, the Ready signal (Q = 1) will indicate (if S
is driven high)that theST93C56is readyto receive
a newinstruction.
Write All
The Write All instruction (WRAL) writes the Data
Input byte or word to all the addresses of the
memory. IftheST93C56is stillperformingthe write
cycle, the Busy signal (Q = 0) will be returned if S
is driven high, and the ST93C56 will ignore any
dataonthebus.Whenthewritecycle iscompleted,
the Ready signal (Q = 1) will indicate (if S is driven
high) that the ST93C56is ready to receive a new
instruction.
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRALor ERALinstruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory when the Chip Select (S) is driven High.
Once the ST93C56 is Ready, the Ready/Busy
status is available on the Data Output (Q) until a
new start bit is decoded or the Chip Select (S) is
broughtLow.
COMMON I/O OPERATION
TheDataOutput(Q)andDataInput(D)signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memorywith this connection,mostly to prevent
a shortcircuit betweenthe last enteredaddressbit
(A0) and the first data bit output by Q. The reader
may also refer to the SGS-THOMSONapplication
note”MICROWIREEEPROMCommonI/OOpera-
tion”.
DIFFERENCES BETWEEN ST93C56 AND
ST93C56C
The ST93C56C is an enhanced version of the
ST93C56 and offers a functional security filtering
glitches on the clockinput (C).
The followingdescriptionwilldetailthe Clock pulse
counter(available only on the ST93C56C).
In a normal environment, the ST93C56expects to
receive the exact amount of data on the D input,
that is, the exact amount of clock pulses on the C
input.
In a noisy environment, the number of pulses re-
ceived (on the clock input C) may be greater than
the clockpulsesdeliveredbytheMaster(Microcon-
troller) driving the ST93C56C. In such a case, a
part of the instruction is delayed by one bit (see
Figure 9), and it may inducean erroneouswrite of
data at a wrongaddress.
The ST93C56C has an on-chip counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 20 (with
the Organisation by 8) from the Start bit to the
fallingedge ofChipSelect signal(1 Startbit+2bits
of Op-code+ 9 bits of Address + 8 bits of Data =
20): if so, the ST93C56C executes the WRITE
instruction; if the number of clock pulses is not
equal to 20, the instruction will not be executed
(and data will not be corrupted).
In the same way, when the Organisationby 16 is
selected, the number of clock pulses incoming to
the countermust be exactly 27 (1 Startbit + 2 bits
of Op-code+ 8 bits of Address + 16 bits of Data =
27) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C56C executes the
WRITE instruction;if thenumber of clockpulses is
not equalto 27, theinstruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions(WRITE, ERASE, ERAL, WRALL).
9/13
ST93C56/56C, ST93C57C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST93C57B1TR | 2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
| ST93C57M1TR | CONNECTOR ACCESSORY |
| ST93C57M3013TR | 2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
| ST93C56CM1013TR | 2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
| ST93C56CM1TR | 2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST93C57CB1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| ST93C57CB1013TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
| ST93C57CB1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
| ST93C57CB3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| ST93C57CB3013TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
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