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參數資料
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
SHCH
t
CSS
Chip Select High to Clock High
50
ns
t
CLSH
t
SKS
Clock Low to Chip SelectHigh
100
ns
t
DVCH
t
DIS
Input Valid to Clock High
100
ns
t
CHDX
t
DIH
Clock High to Input Transition
Temp. Range: grade 1
100
ns
Temp. Range:
grades 3, 6
200
ns
t
CHQL
t
PD0
Clock High to Output Low
500
ns
t
CHQV
t
PD1
Clock High to Output Valid
500
ns
t
CLSL
t
CSH
Clock Low to Chip SelectLow
0
ns
t
SLCH
Chip Select Low to Clock High
250
ns
t
SLSH
t
CS
Chip Select Low to Chip Select High
Note 1
250
ns
t
SHQV
t
SV
Chip Select High to Output Valid
500
ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z
ST93C46A
300
ns
ST93C46C, 47C
200
ns
t
CHCL
t
SKH
Clock High to Clock Low
Note 2
250
ns
t
CLCH
t
SKL
Clock Low to Clock High
Note 2
250
ns
t
W
t
WP
Erase/Write Cycle time
10
ms
f
C
f
SK
Clock Frequency
0
1
MHz
Notes:
1. Chip Selectmust bebrought low for a minimumof 250 ns(t
) between consecutive instruction cycles.
2. The Clock frequency specification calls for aminimum clock period of 1
μ
s, therefore the sum of the timings t
CHCL
+ t
CLCH
must be greater or equal to 1
μ
s. For example, ift
CHCL
is 250 ns, then t
CLCH
must be at least 750ns.
Table 5. ACCharacteristics
(T
A
= 0 to70
°
C or –40 to 85
°
C; V
CC
= 4.5V to 5.5Vor 3V to 5.5V)
AI01428
C
OP CODE
OP CODE
START
S
D
OP CODE INPUT
START
tDVCH
tSHCH
tCLSH
tCHCL
tCLCH
tCHDX
Figure4. Synchronous Timing, Start and Op-CodeInput
4/13
ST93C46A/46C/46T, ST93C47C/47T
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