參數(shù)資料
型號(hào): ST92F250JV9QC
廠商: 意法半導(dǎo)體
英文描述: Aluminum Electrolytic Radial Leaded Low Profile Capacitor; Capacitance: 3300uF; Voltage: 35V; Case Size: 20x25 mm; Packaging: Bulk
中文描述: 16位產(chǎn)品單電壓閃存MCU的家庭的RAM,EEPROM的E3展TMEMULATED,可以2.0b和J1850 BLPD
文件頁數(shù): 108/426頁
文件大?。?/td> 3831K
代理商: ST92F250JV9QC
108/426
ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS
(Cont’d)
INTERRUPT MASK REGISTER HIGH (SIMRH)
R245 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:1 = Reserved.
Bit 0 =
IMI0
Channel I Mask bit
The IMI0 bit is set and cleared by software to ena-
ble or disable interrupts on channel I0 .
0: Interrupt masked
1: An interrupt is generated if the IPI0 bit is set in
the SIPRH register.
INTERRUPT MASK REGISTER LOW (SIMRL)
R246 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:0 =
IMxx
Channel E to H Mask bits
The IMxx bits are set and cleared by software to
enable or disable on channel xx interrupts.
0: Interrupt masked
1: An interrupt is generated if the corresponding
IPxx bit is set in the SIPRL register.
INTERRUPT TRIGGER EVENT REGISTER
HIGH (SITRH)
R247 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:1 = Reserved.
Bit 0 =
ITEI0
Channel I0 Trigger Event
This bit is set and cleared by software to define the
polarity of the channel I0 trigger event
0: The I0 pending bit will be set on the falling edge
of the interrupt line
1: The I0 pending bit will be set on the rising edge
of the interrupt line
Note:
The ITEI0 bit must be set to enable the SCI-
A interrupt as the SCI-A interrupt event is a rising
edge event.
INTERRUPT TRIGGER EVENT REGISTER LOW
(SITRL)
R248 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:0 =
ITExx
Channel E to H Trigger Event
The ITExx bits are set and cleared by software to
define the polarity of the channel xx trigger event
0: The corresponding pending bit will be set on the
falling edge of the interrupt line
1: The corresponding pending bit will be set on the
rising edge of the interrupt line
Note:
The ITExx bits must be set to enable the
CAN interrupts as the CAN interrupt events are ris-
ing edge events.
Note:
If either a rising or a falling edge occurs on
the interrupt lines during a write access to the
ITER register, the pending bit will not be set.
INTERRUPT
(SIPRH)
R249 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
PENDING
REGISTER
HIGH
Bits 7:1 = Reserved.
Bit 0 =
IPI0
Channel I0 Pending bit
The IPI0 bit is set by hardware on occurrence of
the trigger event. (as specified in the ITR register)
and is cleared by hardware on interrupt acknowl-
edge.
0 : No interrupt pending
1 : Interrupt pending
7
0
-
-
-
-
-
-
-
IMI0
7
0
IMH1
IMH0
IMG1
IMG0
IMF1
IMF0
IME1
IME0
7
0
-
-
-
-
-
-
-
ITEI0
7
0
ITEH1 ITEH0 ITEG1 ITEG0
ITEF1
ITEF0
ITEE1
ITEE0
7
0
-
-
-
-
-
-
-
IPI0
9
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