
April 2002
1/12
This is preliminary information on a new product now in development. Details are subject to change without notice.
Rev. 1.1
ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E3TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
DATA BRIEFING
s
Memories
– Internal Memory: Single Voltage FLASH up to 256
Kbytes, RAM up to 8Kbytes, 1K byte E3TM (Emulat-
ed EEPROM)
– In-Application Programming (IAP)
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
s
Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 80 ns (25 MHz int. clock)
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Interrupt Management
– 80, 77 or 48 I/O pins (depending on device)
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
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Timers
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
er (activated by software or by hardware)
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
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Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
(on 100-pin versions only)
– J1850 Byte Level Protocol Decoder (JBLPD)
(on F150J versions only)
– One or two full I C multiple Master/Slave Interfaces
supporting Access Bus
– One or two CAN 2.0B (150 version only) Active inter-
faces with:
– Up to 1 MBit/s communication speed
– 3 Transmit Mailboxes with priority configuration
by software
– Enhanced Filtering mechanism
– 2 prioritized FIFO receive schemes
– Time-Triggered Communication support
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DMA controller for reduced processor overhead
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10-bit Analog to Digital Converter allowing up to 16
input channels on 100-pin devices or 8 input channels
on 64-pin devices
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Instruction Set
– Rich Instruction Set with 14 Addressing Modes
– Division-by-zero trap generation
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Development Tools
– Versatile Development Tools, including Assembler,
Linker, C-Compiler, Source Level Debugger, Real
Time Operating System (OSEK OS, CMX) and CAN
drivers
– Hardware Emulator, Flash Programming Boards
DEVICE SUMMARY
PQFP100
14x20
TQFP64
14x14
TQFP100
14x14
Features
ST92F124R9
ST92F150C(R/V)1
ST92F150JV1 ST92F150JDV1
ST92F250CV2
FLASH - bytes
60K
128K
256K
RAM - bytes
2K
4K
6K
8K
E3TM - bytes
1K
Timers
2 MFT, STIM, WD
2 MFT, 0/2 EFT,
STIM, WD
2 MFT, 2 EFT, STIM, WD
Serial Interface
SCI, SPI, I C
1/2 SCI, SPI, I C
2 SCI, SPI, 2 I C
ADC
8 x 10 bits
8/16 x 10 bits
16 x 10 bits
Network Interface
-
CAN
J1850
2 CAN, J1850
CAN
Temp. Range
-40oCto 85o Cor -40o Cto 125o C
Packages
TQFP64
P/TQF P100 and TQFP 64
PQFP100
P/TQ FP100
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