參數(shù)資料
型號(hào)： ST92F120JV1
英文描述： 8/16-BIT FLASH MCU FAMILY WITH RAM. EEPROM AND J1850 BLPD
中文描述： 16位產(chǎn)品系列閃存微控制器與內(nèi)存。 EEPROM和J1850 BLPD
文件頁(yè)數(shù)： 52/324頁(yè)
文件大?。?/td> 3655K
代理商： ST92F120JV1
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
(231FFDh). The second write access, with Pro-
gram Data matching with NVPWD[1:0] content, re-
sets the PWOK bit of NVWPR.
These two registers can be accessed only in write
mode (a read access returns FFh).
3.6.2 Temporary Unprotection
On user request the memory can be configured so
as to allow the temporary unprotection also of all
access protections bits of NVAPR (write protection
bits of NVWPR are always temporarily unprotecta-
ble).
Bit APEX can be temporarily disabled by execut-
ing the Set Protection operation and writing 1 into
this bit, but only if this write instruction is executed
from an internal memory (Flash and Test Flash ex-
cluded).
Bit APEE can be temporarily disabled by execut-
ing the Set Protection operation and writing 1 into
this bit, but only if this write instruction is executed
from the memory itself to unprotect (EEPROM).
Bits APRO and APBR can be temporarily disabled
through a direct write at NVAPR location, by over-
writing at 1 these bits, but only if this write instruc-
tion is executed from the memory itself to unpro-
tect.
To restore the access protection bits it needs to re-
set the micro or to execute a Set Protection opera-
tion and write 0 into the desired bits.
When an internal memory (Flash, TestFlash or
EEPROM) is protected in access, also the data ac-
cess through a DMA of a peripheral is forbidden (it
returns FFh). To read data in DMA mode from a
protected memory, first it is necessary to tempo-
rarily unprotect that memory.
The temporary unprotection allows also to update
a protected code.
3.7 FLASH IN-SYSTEM PROGRAMMING
The Flash memory can be programmed in-system
through a serial interface (SCI0).
Exiting from reset, the ST9 executes the initializa-
tion from the TestFlash code (written in Test-
Flash), where it checks the value of the SOUT0
pin. If it is at 0, this means that the user wishes to
update the Flash code, otherwise normal execu-
tion continues. In this second case, the TestFlash
code reads the reset vector.
If the Flash is virgin (read content is always FFh),
its reset vector contains FFFFh. This is interpreted
by the TestFlash code as a flag indicating that the
Flash memory is virgin and needs to be pro-
grammed. If the value 1 is detected on the SOUT0
pin and the Flash is virgin, a HALT instruction is
executed, waiting for a hardware Reset.
3.7.1 Code Update Routine
The TestFlash Code Update routine is called auto-
matically if the SOUT0 pin is held low during pow-
er-on.
The Code Update routine performs the following
operations:
I
Enables the SCI0 peripheral in synchronous
mode
I
Transmits a synchronization datum (25h);
I
Waits for an address match (23h) with a timeout
of 10ms (@ f
OSC
4 MHz)
I
If the match is not received before the timeout,
the execution returns to the Power-On routine
I
If the match is received, the SCI0 transmits a
new datum (21h) to tell the external device that
it is ready to receive the data to be loaded in
RAM (that represents the code of the in-system
programming routine).
I
Receives two data representing the number of
bytes to be loaded (max. 4 Kbytes)
I
Receive the specified number of bytes (each
one preceded by the transmission of a Ready to
Receive character: (21h) and writes them in
internal RAM starting from address 200010h.
The first 4 words should be the interrupt vectors
of the 4 possible SCI interrupts, to be used by
the in-system programming routine.
I
Transmit a last datum (21h) as a request for end
of communications.
I
Receives
the
end
confirmation datum (any byte other than 25h).
I
Resets all the unused RAM locations to FFh;
I
Calls address 200018h in internal RAM.
I
After completion of the in-system programming
routine, an HALT instruction is executed and an
Hardware Reset is needed.
The Code Update routine initializes the SCI0 pe-
ripheral as shown in the following table:
of
communication
Table 12. SCI0 Registers (page 24) initialization
Register
IVR - R244
ACR - R245
IDPR - R249
CHCR - R250
Value
10h
23h
00h
83h
Notes
Vector Table in 0010h
Address Match is 23h
SCI interrupt priority is 0
8 Data Bits
rec. clock: ext RXCLK0
trx clock: int CLKOUT0
CCR - R251
E8h
BRGHR - R252
00h
9
相關(guān)PDF資料
PDF描述
ST92F120JV9 8/16-BIT FLASH MCU FAMILY WITH RAM. EEPROM AND J1850 BLPD
ST92F120V1 8/16-BIT FLASH MCU FAMILY WITH RAM. EEPROM AND J1850 BLPD
ST92F150JD ST9 - 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM. E3 TM (EMULATED EEPROM). CAN 2.0B AND J1850 BLPD
ST92F150JV1 Microcontroller
ST93C06CB1 Microwire Serial EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST92F120V1Q7 功能描述:8位微控制器 -MCU Flash 128K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92F120V9Q7 功能描述:8位微控制器 -MCU RO 511-ST92F150CV1QB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92F124R9TB 功能描述:8位微控制器 -MCU Flash 64K SCI/SPI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92F124V1QB 功能描述:8位微控制器 -MCU Flash 128K 2SCI/SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST92F124V1T6 功能描述:8位微控制器 -MCU 8/16-BIT SINGLE VOLT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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