參數(shù)資料
型號： ST92195D5T1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQFP64
封裝： TQFP-64
文件頁數(shù)： 103/250頁
文件大小： 3010K
代理商： ST92195D5T1/XXX
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ST92195 ST92T195 ST92E195 - TWO-CHANNEL I2C BUS INTERFACE (I2C)
I2C BUS INTERFACE (Cont’d)
CONTROL REGISTER (I2CCTR)
R242 - Read/Write
Register Page: 44
Reset Value: 0000 0001(01h)
Bit 7 = AFEN
Advanced Features Enable bit
This bit enables or disables the unexpected & un-
processed error detection. Refer to the description
of the UNPROC and UNEXP bits in the I2CSTR2
register.
0: Advanced features disabled
1: Advanced features enabled
Bit 6 = RTI
Return To Inactive state bit
This bit determines the interface status after an in-
terrupt is processed (either after a complete trans-
fer or an error occured).
0: The interface keeps its active state
1: The interface (master or slave) returns to the in-
active slave state
Note: The state of the Active Flag (I2CSTR1.0) is
maintained.The RTI bit is automatically cleared.
Bit 5 = GENC_ACK
General Call Acknowledge bit
This bit determines the response of the I2C inter-
face when a general call is detected on the bus.
0: The interface will acknowledge the reception of
a ‘General Call’ immediately after receiving the
address 00h. An interrupt is generated at the
end of the acknowledge interval that follows the
address.
1: The interface will not acknowledge a ‘General
Call’ and does not generate an interrupt, i.e.
the interface will remain an inactive slave.
Bit 4 = SEND_ACK
Send Acknowledge bit
This bit is set by software to define if the acknowl-
edge bit is placed on the bus when the interface is
operating as a master receiver, active slave re-
ceiver or an active slave.
0: An inactive interface will acknowledge the re-
ception of its address and switch to active slave
mode.
1: The interface will not acknowledge the reception
of its address and remains inactive.
Note: The interface operating as a master slave
receiver is free to acknowledge or not all data
bytes. In a normal I2C transaction, it acknowledg-
es all data bytes except the last received from a
slave/master transmitter.
SEND_ACK should be programmed before receiv-
ing the relevant byte (data or address).
Bit 3 = MONITOR
Bus Monitor mode bit
This bit determines if the interface acts as a bus
monitor or not.
0: The bus monitor mode is disabled.
1: The interface behaves as a bus monitor. The in-
terface becomes a slave regardless of the ad-
dress received, but neither the address or the
following data is acknowledged (this is equiva-
lent to SEND_ACK=1). If a read address is re-
ceived, the high state of the least significant bit
of this address is suppressed inside the inter-
face and all data bytes are processed by the
MCU as received data.
Bit 2 = RSRT
Repeated Start bit
This bit determines if the interface generates auto-
matically a repeated start condition on the I2C bus
(in master mode) as soon as a new byte is ready to
be send.
0: Repeated start disabled
1: Repeated start enabled
Note: This bit is automatically cleared.
Bit 1 = STOP
STOP condition generation bit
When working in master mode, this bit enables or
disables a STOP condition generation on the I2C
bus.
0: No Stop condition is generated
1: The master will generate a stop condition to ter-
minate the bus transaction. The master will au-
tomatically revert to an inactive slave and the
STOP bit will be cleared.
Bit 0 = CLEAR
Clear interface bit
This bit enables or disables the I2C interface.
0: The interface is enabled
1: A general reset is generated. The interface be-
comes an inactive slave and the SCL and SDA
buses drive signals are removed. The system
is kept in reset state until the CLEAR bit is writ-
ten to “0”.
Note: The CLEAR bit is “1” (i.e. the interface is dis-
abled) when exiting from the MCUs power-on re-
set state.
70
AFEN RTI
GENC_
ACK
SEND_
ACK
MONI
TOR
RSRT STOP CLEAR
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