參數(shù)資料
型號(hào)： ST92163N4
英文描述： 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS. 20K ROM. 2K RAM. I 2 C. SCI. & MFT
中文描述： 16位產(chǎn)品全速USB微控制器，16終點(diǎn)復(fù)合設(shè)備。 20,000光盤。 2K的RAM。余2長(zhǎng)脊髓損傷。
文件頁(yè)數(shù)： 132/230頁(yè)
文件大?。?/td> 2743K
代理商： ST92163N4
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ST92163 - MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER
(Cont’d)
FLAG REGISTER (T_FLAGR)
R254 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
Bit
7 =
CP0
:
Capture 0 flag.
This bit is set by hardware after a capture on
REG0R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP0 bit must be cleared by software.
Setting by software acts as a software load/cap-
ture to/from the REG0R register.
0: No Capture 0 event
1: Capture 0 event occurred
Bit 6 =
CP1
:
Capture 1 flag
.
This bit is set by hardware after a capture on
REG1R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP1 bit must be cleared by software.
Setting by software acts as a capture event on the
REG1R register, except when in Bicapture mode.
0: No Capture 1 event
1: Capture 1 event occurred
Bit 5 =
CM0
:
Compare 0 flag
.
This bit is set by hardware after a successful com-
pare on the CMP0R register. An interrupt is gener-
ated if the GTIEN and CM0I bits in the IDMR reg-
ister are set. The CM0 bit is cleared by software.
0: No Compare 0 event
1: Compare 0 event occurred
Bit 4 =
CM1
:
Compare 1 flag.
This bit is set after a successful compare on
CMP1R register. An interrupt is generated if the
GTIEN and CM1I bits in the IDMR register are set.
The CM1 bit is cleared by software.
0: No Compare 1 event
1: Compare 1 event occurred
Bit 3 =
OUF
:
Overflow/Underflow
.
This bit is set by hardware after a counter Over/
Underflow condition. An interrupt is generated if
GTIEN and OUI=1 in the IDMR register. The OUF
bit is cleared by software.
0: No counter overflow/underflow
1: Counter overflow/underflow
Bit 2 =
OCP0
:
Overrun on Capture 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CP0 flag is
cleared by software or whenever a capture is sim-
ulated by setting the CP0 flag by software. The
OCP0 flag is cleared by software.
0: No capture 0 overrun
1: Capture 0 overrun
Bit 1 =
OCM0
:
Overrun on compare 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CM0 flag is
cleared by software.The OCM0 flag is cleared by
software.
0: No compare 0 overrun
1: Compare 0 overrun
Bit 0 =
A0
:
Capture interrupt function
.
This bit is set and cleared by software.
0: Configure the capture interrupt as an OR func-
tion of REG0R/REG1R captures
1: Configure the capture interrupt as an AND func-
tion of REG0R/REG1R captures
Note:
When A0 is set, both CP0I and CP1I in the
IDMR register must be set to enable both capture
interrupts.
7
0
CP0
CP1
CM0
CM1
OUF
OCP
0
OCM
0
A0
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