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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 60. ST92F124/F150/F250 Clock Distribution Diagram
CLOCK1
PLL
x
1/16
1/2
DIV2
1/ N
MX(1:0)
CSU_CKSEL
6/8/10/14
XT_DIV16
DX(2:0)
1/4
CK_128
0
1
0
1
RCCU
INTCLK
CLOCK2
STIM
1/4
8
1
C
1...256
3-bit Prescaler
CPU
MFTx
1/3
8
1
C
1...256
(TxINA/TxINB
EFTx
1/N
1
C
EXTCLKx
(Max INTCLK/4)
N=2,4,8
Baud Rate
Generator
1/N
N = 2...(2
16
-1)
SCI-M
3
1...8
Baud Rate
Generator
1/N
N=2,4,16,32
SCK
Master
SCK
Slave
(Max INTCLK/2)
SPI
LOGIC
JBLPD
CPUCLK
EMBEDDED MEMORY
RAM
EPROM
FLASH
E
3 TM
I
2
C
STD
FAST
1/N
1/N
N=4,6,8...258
N=6,9,12...387
Fscl
≤
100 kHz
≤
400 kHz
Fscl
1...8
SCI-A
6
1...64
P6.5
1/2
1/16
P6.0
1/8
P4.1
1
C
1/4
WDG
8
1...256
J
CKAF_SEL
0
1
0
1
CK_AF
2
ADC
3-bit Prescaler
1...8
3
3
8
8
1,3,4,13
1...128
1...256
CAN
Baud Rate
Prescaler
1...64
WDIN
CLOCK2/8
P7.0
1/2
9