參數(shù)資料
型號(hào): ST901
廠商: 意法半導(dǎo)體
英文描述: HIGH VOLTAGE IGNITION COIL DRIVER NPN POWER DARLINGTON
中文描述: 高壓點(diǎn)火線圈驅(qū)動(dòng)達(dá)林頓NPN電源
文件頁數(shù): 164/199頁
文件大小: 2813K
代理商: ST901
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁當(dāng)前第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁
164/199
ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
INTERRUPT/DMA PRIORITY REGISTER (IDPR)
R249 - Read/Write
Reset value: undefined
Bit 7 =
AMEN
:
Address Mode Enable.
This bit, together with the AM bit (in the CHCR reg-
ister), decodes the desired addressing/9th data
bit/character match operation.
In Address mode the SCI monitors the input serial
data until its address is detected
Note:
Upon reception of address, the RXAP bit (in
the Interrupt Status Register) is set and an inter-
rupt cycle can begin. The address character will
not be transferred into the Receiver Buffer Regis-
ter but all data following the matched SCI address
and preceding the next address word will be trans-
ferred to the Receiver Buffer Register and the
proper interrupts updated. If the address does not
match, all data following this unmatched address
will not be transferred to the Receiver Buffer Reg-
ister.
In any of the cases the RXAP bit must be reset by
software before the next word is transferred into
the Buffer Register.
When AMEN is reset and AM is set, a useful char-
acter search function is performed. This allows the
SCI to generate an interrupt whenever a specific
character is encountered (e.g. Carriage Return).
Bit 6 =
SB
:
Set Break
.
0: Stop the break transmission after minimum
break length.
1: Transmit a break following the transmission of all
data in the Transmitter Shift Register and the
Buffer Register.
Note:
The break will be a low level on the transmit-
ter data output for at least one complete word for-
mat. If software does not reset SB before the min-
imum break length has finished, the break condi-
tion will continue until software resets SB. The SCI
terminates the break condition with a high level on
the transmitter data output for one transmission
clock period.
Bit 5 =
SA
:
Set Address
.
If an address/9th data bit mode is selected, SA val-
ue will be loaded for transmission into the Shift
Register. This bit is cleared by hardware after its
load.
0: Indicate it is not an address word.
1: Indicate an address word.
Note:
Proper procedure would be, when the
Transmitter Buffer Register is empty, to load the
value of SA and then load the data into the Trans-
mitter Buffer Register.
Bit 4 =
RXD
:
Receiver DMA Mask
.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
receiver End of Block interrupt can occur.
0: Disable Receiver DMA request (the RXDP bit in
the S_ISR register can request an interrupt).
1: Enable Receiver DMA request (the RXDP bit in
the S_ISR register can request a DMA transfer).
Bit 3 =
TXD
:
Transmitter DMA Mask
.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
transmitter End Of Block interrupt can occur.
0: Disable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request an interrupt).
1: Enable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request a DMA trans-
fer).
Bit 2:0 =
PRL[2:0]
:
SCI Interrupt/DMA Priority bits
.
The priority for the SCI is encoded with
(PRL2,PRL1,PRL0). Priority level 0 is the highest,
while level 7 represents no priority.
When the user has defined a priority level for the
SCI, priorities within the SCI are hardware defined.
These SCI internal priorities are:
7
0
AMEN
SB
SA
RXD
TXD
PRL2
PRL1
PRL0
AMEN
0
0
AM
0
1
Address interrupt if 9th data bit = 1
Address interrupt if character match
Address interrupt if character match
and 9th data bit =1
Address interrupt if character match
with word immediately following Break
1
0
1
1
Receiver DMA request
Transmitter DMA request
Receiver interrupt
Transmitter interrupt
highest priority
lowest priority
9
相關(guān)PDF資料
PDF描述
ST901T HIGH VOLTAGE IGNITION COIL DRIVER NPN POWER DARLINGTON
ST9291J7B1 Microcontroller
ST9291N2B1 Microcontroller
ST9291N3B1 Microcontroller
ST9291N4B1 Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST9011 制造商:SEMTECH_ELEC 制造商全稱:SEMTECH ELECTRONICS LTD. 功能描述:NPN Silicon Epitaxial Planar Transistor
ST9012 制造商:SEMTECH_ELEC 制造商全稱:SEMTECH ELECTRONICS LTD. 功能描述:PNP Silicon Epitaxial Planar Transistor
ST90-125L2KI 功能描述:CAP TANT 90UF 125V 10% AXIAL RoHS:否 類別:電容器 >> 鉭 系列:SuperTan® ST 標(biāo)準(zhǔn)包裝:1,000 系列:TANTAMOUNT® 695D 電容:3.3µF 電壓 - 額定:50V 容差:±20% ESR(等效串聯(lián)電阻):3.2 歐姆 類型:保形涂層 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:2414(6034 公制) 尺寸/尺寸:0.236" L x 0.135" W(6.00mm x 3.43mm) 高度 - 座高(最大):0.085"(2.16mm) 引線間隔:- 制造商尺寸代碼:F 特點(diǎn):通用 包裝:帶卷 (TR) 壽命@溫度:-
ST9013 制造商:SEMTECH_ELEC 制造商全稱:SEMTECH ELECTRONICS LTD. 功能描述:NPN Silicon Epitaxial Planar Transistor
ST90135 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM