參數(shù)資料
型號(hào): ST72P621J4B1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: PLASTIC, SDIP-32
文件頁數(shù): 89/136頁
文件大小: 2475K
代理商: ST72P621J4B1
ST7262
56/136
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 43) but master and slave
must be programmed with the same timing mode.
Figure 40. Single Master/ Single Slave Application
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
SCK
SLAVE
MASTER
SS
+5V
MSBit
LSBit
MSBit
LSBit
Not used if SS is managed
by software
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