參數(shù)資料
型號(hào)： ST72P60E2M1
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件頁(yè)數(shù)： 57/118頁(yè)
文件大?。?/td> 2304K
代理商： ST72P60E2M1
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ST7260
43/117
16-BIT TIMER (Cont’d)
11.2.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are two input capture functions in the 16-bit
timer.
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see Figure 28).
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (
fCPU/CC[1:0]).
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 17,
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 29).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The two input capture functions can be used
together even if the timer also uses the two out-
put compare functions.
4. In One Pulse mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 and ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
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