參數(shù)資料
型號(hào): ST72F340S2T6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, LEAD FREE, LQFP-44
文件頁數(shù): 39/191頁
文件大?。?/td> 3285K
代理商: ST72F340S2T6
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ST72340, ST72344, ST72345
133/191
Notes:
– The Status Register has to be read to clear the
event flag associated with the interrupt
– An interrupt will be generated only if the interrupt
enable bit is set in the Control Register
– Slaves 1 and 2 have a common interrupt and the
Slave 3 has a separate interrupt.
– At the end of write operation, I2C3S is temporar-
ily disabled by hardware by setting BusyW bit in
CR2. The byte count register, status register and
current address register should be saved before
resetting BusyW bit.
.
11.7.5.1 Slave Reception (Write operations)
Byte Write: The Slave address is followed by an
8-bit byte address. Upon receipt of this address an
acknowledge is generated, address is moved into
the current address register and the 8 bit data is
clocked in. Once the data is shifted in, a DMA
request is generated and the data is written in the
RAM. The addressing device will terminate the
write sequence with a stop condition. Refer to
Page Write: A page write is initiated in similar way
to a byte write, but the addressing device does not
send a stop condition after the first data byte. The
page length is programmed using bits 7:6 (PL[1:0])
in the Control Register1.
The current address register value is incremented
by one every time a byte is written. When this
address reaches the page boundary, the next byte
will be written at the beginning of the same page.
Refer to Figure 74.
11.7.5.2 Slave Transmission (Read Operations)
Current Address Read: The current address
register maintains the last address accessed
during the last read or write operation incremented
by one.
During this operation the I2C slave reads the data
pointed by the current address register. Refer to
Random Read: Random read requires a dummy
byte write sequence to load in the byte address.
The addressing device then generates restart
condition and resends the device address similar
to current address read with the read/write bit high.
Refer to Figure 76. Some types of I2C masters
perform a dummy write with a stop condition and
then a current address read.
In either case, the slave generates a DMA request,
sends an acknowledge and serially clocks out the
data.
When the memory address limit is reached the
current address will roll over and the random read
will continue till the addressing master sends a
stop condition.
Sequential Read: Sequential reads are initiated
by either a current address read or a random
address
read.
After
the
addressing
master
receives the data byte it responds with an
acknowledge. As long as the slave receives an
acknowledge it will continue to increment the
current address register and clock out sequential
data bytes.
When the memory address limit is reached the
current address will roll over and the sequential
read will continue till the addressing master sends
a stop condition. Refer to Figure 78
11.7.5.3 Combined Format:
If a master wants to continue communication
either with another slave or by changing the
direction of transfer then the master would
generate a restart and provide a different slave
address or the same slave address with the R/W
bit reversed. Refer to Figure 79.
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