參數(shù)資料
型號(hào)： ST72F321J9T5
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, PLASTIC, TQFP-44
文件頁(yè)數(shù)： 8/176頁(yè)
文件大?。?/td> 1112K
代理商： ST72F321J9T5
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ST72321J
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.7 Register Description
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 7 = TDRE
Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data will not be transferred to the shift reg-
ister unless the TDRE bit is cleared.
Bit 6 = TC
Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Bit 5 = RDRF
Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE
Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
Bit 3 = OR
Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
Bit 2 = NF
Noise flag.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
Bit 1 = FE
Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
Bit 0 = PE
Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
70
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST72F321J9T6 功能描述:8位微控制器 -MCU Flash 60K SPI/SCI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F321J9TA 功能描述:8位微控制器 -MCU AUTO 8BIT MICRO RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F321J9TAE 功能描述:8位微控制器 -MCU 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F321J9TAS 制造商:STMicroelectronics 功能描述:
ST72F321J9TC 功能描述:8位微控制器 -MCU Flask 60K SPI/SCI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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