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參數(shù)資料
| 型號(hào)： | ST72121J2T6/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁(yè)數(shù)： | 22/87頁(yè) |
| 文件大?。?/td> | 1365K |
| 代理商： | ST72121J2T6/XXX |
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ST72121
4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
4.2.2 Main Features
Programmable timer (64 increments of 12288
CPU cycles)
Programmable reset
Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Hardware Watchdog selectable by option byte.
Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
Figure 19. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
fCPU
T6
T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷12288
T1
T2
T3
T4
T5
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