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參數(shù)資料
| 型號： | ST6x86 |
| 廠商： | 意法半導體 |
| 英文描述： | P90+, P120+, P133+, P150+, P166+ 3.52 Volt ST6x86 CPU(P90+, P120+, P133+, P150+, P166+ 3.52 V CPU) |
| 中文描述： | P90，P120的，P133，P150，166頁3.52伏特ST6x86的CPU（P90，P120的，P133，P150，166頁3.52 V中央處理器） |
| 文件頁數(shù)： | 1/53頁 |
| 文件大?。?/td> | 406K |
| 代理商： | ST6X86 |
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ST6x86
P90+, P120+, P133+, P150+, P166+
3.52 Volt ST6x86 CPU
BLOCK DIAGRAM
August 1996
1/53
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PRELIMINARY DATA
The ST6x86
microprocessor is a superscalar,
superpipelined CPU that provides sixth-generation
performance for x86 software. Since the ST6x86
CPU is fully compatible with the x86 instruction
set,it is capable of executing a wide range of exist-
ing operating systems and applications, including
Windows 95, DOS, Unix, Windows NT, Novell,
OS/2, and Solaris. The ST6x86 CPU achieves top
performance levels through the use of two opti-
mized superpipelined integer units and an on-chip
floatingpoint unit. The superpipelined architecture
reduces timing constraints and allows the ST6x86
CPU to achieve P90+ performance levels and
above. In addition, the ST6x86 CPU’s integer and
floating point units are optimized for maximum
instruction throughput by using advanced architec-
tural techniques, including register renaming,
out-of-order execution, data forwarding, branch
prediction, and speculative execution.
design innovations eliminate many data depen-
dencies and resource conflicts that provide opti-
mum performance for Windows 95 software.
These
Sixth-Generation Superscalar Superpipelined
Architecture
- Dual 7-stage integer pipelines
- High performance on-chip FPU with 64-bit
interface
- Operating at P90+ speeds and above
- 16-KByte write-back cache
X86 Instruction Set Compatible
- Runs Windows 95, Windows NT, DOS, UNIX,
Novell,OS/2, Solaris, and others
Optimum Performance for Windows
95
- Intelligent instruction dispatch
- Out-of-order execution
- Register renaming
- Data forwarding
- Branch prediction
- Speculative execution
64-Bit Data Bus
- P54C socket compatible for quick time to
market
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6X86P120+HS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST6X86P133+HS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST6X86P150+HS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST6X86P166+HS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| ST6XXX-EMU2 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST6 MCU FAMILY |
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