參數(shù)資料
型號(hào): ST63T69B1
廠商: 意法半導(dǎo)體
英文描述: 8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCYMONITOR
中文描述: 8位HCMOS單片機(jī)的數(shù)控多FREQUENCYMONITOR
文件頁(yè)數(shù): 12/71頁(yè)
文件大?。?/td> 584K
代理商: ST63T69B1
ST6369 CORE
(Continued)
Stack
The ST6369 Core includes true LIFO hardware
stack that eliminates the need for a stackpointer.
The stackconsistsofsix separate12-bit RAM loca-
tions that do not belong to the data space RAM
area. When a subroutine call (or interruptrequest)
occurs,the contentsofeach levelis shiftedinto the
next levelwhile the contentof the PCis shiftedinto
the first level (the value of the sixth level will be
lost). When subroutine or interrupt return occurs
(RET orRETI instructions),thefirst levelregisteris
shifted backintothe PCand thevalueof eachlevel
is shifted back into the previous level. These two
operating modes are described in Figure 5. Since
the accumulator,as all otherdata space registers,
is notstored inthisstack thehandlingof thisregis-
ters shall be performed inside the subroutine. The
stack pointer will remain in its deepest position,if
more than 6 calls or interrupts are executed, so
that the last return address will be lost. It will also
remain in its highest position if the stack is empty
and a RET or RETI is executed. In this case the
next instruction will be executed.
Memory Registers
The PRPR
can be addressed like a RAM location
in the Data Space at the CAH address; neverthe-
less it is a write-only register that can not be ac-
cessed with single-bit operations.This register is
used to select the 2-Kbyte ROM bank of the Pro-
gram Spacethat will be addressed.The numberof
the page hastobe loaded inthePRPR. ThePRPR
is not cleared during the MCU initialization and
should therefore be definedbefore jumping out of
the static page. Refer to the Program Space de-
scription for additional information concerning the
use of this register. The PRPR is not modified
when an interrupt or a subroutine occurs.
PRPR
Program ROMPage Register
(CAH, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Figure6. Program ROMPage Register
DRBR
Data RAM Bank Register
(E8H, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. Data RAM Bank Register
DRWR
Data ROM Window Register
(C9H, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 8. Data ROM Window Register
The DRBR
can be addressedlike a RAMlocation
in the Data Space at the E8H address, neverthe-
less it is write-only register that can not be ac-
cessed with single-bit operations. This register is
used to select the desired 64-byteRAM/EEPROM
bank of the Data Space. The number of the bank
has to be loaded in the DRBR and the instruction
has to point tothe selected locationasit was in the
0 bank (from 00H address to 3FH address). This
register isundefined afterReset. Refer to the Data
Space description for additional information. The
DRBR register is not modifiedwhen a interrupt or
a subroutineoccurs.
TheDRWR
registercanbeaddressedlikeaRAMlo-
cationin theDataSpaceat the C9Haddress,never-
theless it is write-only register that can not be
accessed with single-bit operations.This register is
used to move up and down the 64-byte read-only
datawindow(from the40H addressto 7FH address
of the Data Space) along the ROM of the MCU by
stepof 64bytes.The effectiveaddressof thebyteto
bereadasadatainthe ROMisobtainedbythecon-
catenationofthe6lesssignificantbitsoftheaddress
given in the instruction (as less significant bits) and
the content of the DRWR (as most significant
bits). Refer to the Data Space descriptionfor addi-
tionalinformation.
ST6369
8/67
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