參數(shù)資料
型號： ST62T28C
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
中文描述： 8位單片機與微控制器/ D轉(zhuǎn)換器，自動重加載定時器，UART的秘書長辦公室，安全復(fù)位和28引腳封裝
文件頁數(shù)： 50/84頁
文件大?。?/td> 561K
代理商： ST62T28C
50/84
50
ST62T28C/E28C
4.4 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converterwith analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of 12 or 6. AfterReset, division by 12is used
by default to insure compatibility with other mem-
bers of the ST62 MCU family. With an oscillator
clock frequency less than 1.2MHz, conversion ac-
curacy is decreased.
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
The ADC uses two registersin the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write onlybit, anyattempt to read it will show a log-
ical “0”.
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done bysetting the PDS bit in theADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered anden-
abled for conversion. This bit must be set at least
one instruction before thebeginning of the conver-
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, thecontrol register is reset to 40h and the
ADC interrupt is masked (EAI=0).
Figure 29. ADC Block Diagram
4.4.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±
1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
When selected asan analog channel, the input pin
is internally connected to a capacitor C
ad
of typi-
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5
μ
s) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
6.5
μ
s = 9 x C
ad
x ASI
(capacitor charged to over 99.9%), i.e. 30 k
in-
cluding a 50% guardband. ASI can behigher if C
ad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
CONTROL REGISTER
CONVERTER
VA00418
RESULT REGISTER
RESET
AV
AV
DD
INTERRUPT
CLOCK
Ain
8
CORE
CONTROL SIGNALS
SS
8
CORE
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