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參數(shù)資料
| 型號： | ST62P45BQ6/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 18/72頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ST62P45BQ6/XXX |
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ST62T45B/E45B
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
Address: 0D8h
—
Read/Write
Reset status: 1111 1110b
Bit 0 = C:
Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When C is kept low the counter can be used as a
7-bit timer.
This bit is cleared to “0” on Reset.
Bit 1 = SR:
Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0:
Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
These bits are set to “1” on Reset.
3.3.2 Application Notes
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
When STOP mode is not required, hardware acti-
vation should be preferred, as it provides maxi-
mum security, especially during power-on.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH
70
T0
T1
T2
T3
T4
T5
SR
C
24
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