參數(shù)資料
型號(hào)： ST52514G3
英文描述： IC MAX 7000 CPLD 64 100-TQFP
中文描述： 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁數(shù)： 78/106頁
文件大小： 1355K
代理商： ST52514G3
11.6 PWM/Timer 0 Register Description
The following registers are related to the use of the
PWM/Timer 0.
PWM/Timer 0 Control Register 1 (PWM0_CR1)
Configuration Register 9 (09h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: T0MOD PWM/Timer 0 Mode
0: Timer Mode
1: PWM Mode
Bit 6: T0IES Interrupt on Stop signal Enable
0: interrupt disabled
1: interrupt enabled
Bit 5: T0IEF Interrupt on T0OUT falling Enable
0: interrupt disabled
1: interrupt enabled
Bit 4: T0IER Interrupt on T0OUT rising Enable
0: interrupt disabled
1: interrupt enabled
Bit 3: STRMOD Start signal mode
0: start on level
1: start on edge
Bit 2: T0STRT PWM/Timer 0 Start bit
0: Timer 0 stopped
1: Timer 0 started
Bit 1: RESMOD Reset signal mode
0: reset on level
1: reset on edge
Bit 0: T0RES PWM/Timer 0 Reset bit
0: PWM/Timer 0 reset
1: PWM/Timer 0 set
PWM/Timer 0 Control Register 2 (PWM0_CR2)
Configuration Register 10 (0Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5: T0WAV T0OUT Waveform
0: pulse (type2)
1: square (type1)
Bit 4-0: T0PRESC PWM/Timer 0 Prescaler
The PWM/Timer 0 clock is divided by a
factor equal to 2T0PRESC. The maximum
value allowed for T0PRESC is 10000
(010h).
PWM/Timer 0 Control Register 3 (PWM0_CR3)
Configuration Register 11 (0Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: T0SYNC PWM/Timer 0 Set/Reset mask
0: Set/Reset activated
1: Set/Reset masked
Bit 6: not used
Bit 5: T1SYNC PWM/Timer 1 Set/Reset mask
0: Set/Reset activated
1: Set/Reset masked
Bit 4: T0CKS PWM/Timer 0 Clock Source
0: Internal clock
1: External Clock from TCLK
Bit 3-2: STRSRC PWM/Timer 0 Start signal source
00: Internal from T0STRT bit
01: External from TSTRT pin
10: Both internal and external
70
T0MOD
T0IES
T0IEF
T0IER STRMOD T0STRT RESMOD T0RES
74
0
--
T0WAV
T0PRESC
70
T1SYNC
-
T0SYNC T0CKS
STRSRC
RESSRC
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